hw/arm/npcm7xx.c

   1 /*
   2  * Nuvoton NPCM7xx SoC family.
   3  *
   4  * Copyright 2020 Google LLC
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the
   8  * Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  14  * for more details.
  15  */
  16
  17 #include "qemu/osdep.h"
  18
  19 #include "exec/address-spaces.h"
  20 #include "hw/arm/boot.h"
  21 #include "hw/arm/npcm7xx.h"
  22 #include "hw/char/serial.h"
  23 #include "hw/loader.h"
  24 #include "hw/misc/unimp.h"
  25 #include "hw/qdev-clock.h"
  26 #include "hw/qdev-properties.h"
  27 #include "qapi/error.h"
  28 #include "qemu/units.h"
  29 #include "sysemu/sysemu.h"
  30
  31 /*
  32  * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
  33  * that aren't handled by any device.
  34  */
  35 #define NPCM7XX_MMIO_BA         (0x80000000)
  36 #define NPCM7XX_MMIO_SZ         (0x7ffd0000)
  37
  38 /* OTP key storage and fuse strap array */
  39 #define NPCM7XX_OTP1_BA         (0xf0189000)
  40 #define NPCM7XX_OTP2_BA         (0xf018a000)
  41
  42 /* Core system modules. */
  43 #define NPCM7XX_L2C_BA          (0xf03fc000)
  44 #define NPCM7XX_CPUP_BA         (0xf03fe000)
  45 #define NPCM7XX_GCR_BA          (0xf0800000)
  46 #define NPCM7XX_CLK_BA          (0xf0801000)
  47 #define NPCM7XX_MC_BA           (0xf0824000)
  48 #define NPCM7XX_RNG_BA          (0xf000b000)
  49
  50 /* USB Host modules */
  51 #define NPCM7XX_EHCI_BA         (0xf0806000)
  52 #define NPCM7XX_OHCI_BA         (0xf0807000)
  53
  54 /* ADC Module */
  55 #define NPCM7XX_ADC_BA          (0xf000c000)
  56
  57 /* Internal AHB SRAM */
  58 #define NPCM7XX_RAM3_BA         (0xc0008000)
  59 #define NPCM7XX_RAM3_SZ         (4 * KiB)
  60
  61 /* Memory blocks at the end of the address space */
  62 #define NPCM7XX_RAM2_BA         (0xfffd0000)
  63 #define NPCM7XX_RAM2_SZ         (128 * KiB)
  64 #define NPCM7XX_ROM_BA          (0xffff0000)
  65 #define NPCM7XX_ROM_SZ          (64 * KiB)
  66
  67
  68 /* Clock configuration values to be fixed up when bypassing bootloader */
  69
  70 /* Run PLL1 at 1600 MHz */
  71 #define NPCM7XX_PLLCON1_FIXUP_VAL   (0x00402101)
  72 /* Run the CPU from PLL1 and UART from PLL2 */
  73 #define NPCM7XX_CLKSEL_FIXUP_VAL    (0x004aaba9)
  74
  75 /*
  76  * Interrupt lines going into the GIC. This does not include internal Cortex-A9
  77  * interrupts.
  78  */
  79 enum NPCM7xxInterrupt {
  80     NPCM7XX_ADC_IRQ             = 0,
  81     NPCM7XX_UART0_IRQ           = 2,
  82     NPCM7XX_UART1_IRQ,
  83     NPCM7XX_UART2_IRQ,
  84     NPCM7XX_UART3_IRQ,
  85     NPCM7XX_EMC1RX_IRQ          = 15,
  86     NPCM7XX_EMC1TX_IRQ,
  87     NPCM7XX_TIMER0_IRQ          = 32,   /* Timer Module 0 */
  88     NPCM7XX_TIMER1_IRQ,
  89     NPCM7XX_TIMER2_IRQ,
  90     NPCM7XX_TIMER3_IRQ,
  91     NPCM7XX_TIMER4_IRQ,
  92     NPCM7XX_TIMER5_IRQ,                 /* Timer Module 1 */
  93     NPCM7XX_TIMER6_IRQ,
  94     NPCM7XX_TIMER7_IRQ,
  95     NPCM7XX_TIMER8_IRQ,
  96     NPCM7XX_TIMER9_IRQ,
  97     NPCM7XX_TIMER10_IRQ,                /* Timer Module 2 */
  98     NPCM7XX_TIMER11_IRQ,
  99     NPCM7XX_TIMER12_IRQ,
 100     NPCM7XX_TIMER13_IRQ,
 101     NPCM7XX_TIMER14_IRQ,
 102     NPCM7XX_WDG0_IRQ            = 47,   /* Timer Module 0 Watchdog */
 103     NPCM7XX_WDG1_IRQ,                   /* Timer Module 1 Watchdog */
 104     NPCM7XX_WDG2_IRQ,                   /* Timer Module 2 Watchdog */
 105     NPCM7XX_EHCI_IRQ            = 61,
 106     NPCM7XX_OHCI_IRQ            = 62,
 107     NPCM7XX_SMBUS0_IRQ          = 64,
 108     NPCM7XX_SMBUS1_IRQ,
 109     NPCM7XX_SMBUS2_IRQ,
 110     NPCM7XX_SMBUS3_IRQ,
 111     NPCM7XX_SMBUS4_IRQ,
 112     NPCM7XX_SMBUS5_IRQ,
 113     NPCM7XX_SMBUS6_IRQ,
 114     NPCM7XX_SMBUS7_IRQ,
 115     NPCM7XX_SMBUS8_IRQ,
 116     NPCM7XX_SMBUS9_IRQ,
 117     NPCM7XX_SMBUS10_IRQ,
 118     NPCM7XX_SMBUS11_IRQ,
 119     NPCM7XX_SMBUS12_IRQ,
 120     NPCM7XX_SMBUS13_IRQ,
 121     NPCM7XX_SMBUS14_IRQ,
 122     NPCM7XX_SMBUS15_IRQ,
 123     NPCM7XX_PWM0_IRQ            = 93,   /* PWM module 0 */
 124     NPCM7XX_PWM1_IRQ,                   /* PWM module 1 */
 125     NPCM7XX_EMC2RX_IRQ          = 114,
 126     NPCM7XX_EMC2TX_IRQ,
 127     NPCM7XX_GPIO0_IRQ           = 116,
 128     NPCM7XX_GPIO1_IRQ,
 129     NPCM7XX_GPIO2_IRQ,
 130     NPCM7XX_GPIO3_IRQ,
 131     NPCM7XX_GPIO4_IRQ,
 132     NPCM7XX_GPIO5_IRQ,
 133     NPCM7XX_GPIO6_IRQ,
 134     NPCM7XX_GPIO7_IRQ,
 135 };
 136
 137 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
 138 #define NPCM7XX_NUM_IRQ         (160)
 139
 140 /* Register base address for each Timer Module */
 141 static const hwaddr npcm7xx_tim_addr[] = {
 142     0xf0008000,
 143     0xf0009000,
 144     0xf000a000,
 145 };
 146
 147 /* Register base address for each 16550 UART */
 148 static const hwaddr npcm7xx_uart_addr[] = {
 149     0xf0001000,
 150     0xf0002000,
 151     0xf0003000,
 152     0xf0004000,
 153 };
 154
 155 /* Direct memory-mapped access to SPI0 CS0-1. */
 156 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
 157     0x80000000, /* CS0 */
 158     0x88000000, /* CS1 */
 159 };
 160
 161 /* Direct memory-mapped access to SPI3 CS0-3. */
 162 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
 163     0xa0000000, /* CS0 */
 164     0xa8000000, /* CS1 */
 165     0xb0000000, /* CS2 */
 166     0xb8000000, /* CS3 */
 167 };
 168
 169 /* Register base address for each PWM Module */
 170 static const hwaddr npcm7xx_pwm_addr[] = {
 171     0xf0103000,
 172     0xf0104000,
 173 };
 174
 175 /* Direct memory-mapped access to each SMBus Module. */
 176 static const hwaddr npcm7xx_smbus_addr[] = {
 177     0xf0080000,
 178     0xf0081000,
 179     0xf0082000,
 180     0xf0083000,
 181     0xf0084000,
 182     0xf0085000,
 183     0xf0086000,
 184     0xf0087000,
 185     0xf0088000,
 186     0xf0089000,
 187     0xf008a000,
 188     0xf008b000,
 189     0xf008c000,
 190     0xf008d000,
 191     0xf008e000,
 192     0xf008f000,
 193 };
 194
 195 /* Register base address for each EMC Module */
 196 static const hwaddr npcm7xx_emc_addr[] = {
 197     0xf0825000,
 198     0xf0826000,
 199 };
 200
 201 static const struct {
 202     hwaddr regs_addr;
 203     uint32_t unconnected_pins;
 204     uint32_t reset_pu;
 205     uint32_t reset_pd;
 206     uint32_t reset_osrc;
 207     uint32_t reset_odsc;
 208 } npcm7xx_gpio[] = {
 209     {
 210         .regs_addr = 0xf0010000,
 211         .reset_pu = 0xff03ffff,
 212         .reset_pd = 0x00fc0000,
 213     }, {
 214         .regs_addr = 0xf0011000,
 215         .unconnected_pins = 0x0000001e,
 216         .reset_pu = 0xfefffe07,
 217         .reset_pd = 0x010001e0,
 218     }, {
 219         .regs_addr = 0xf0012000,
 220         .reset_pu = 0x780fffff,
 221         .reset_pd = 0x07f00000,
 222         .reset_odsc = 0x00700000,
 223     }, {
 224         .regs_addr = 0xf0013000,
 225         .reset_pu = 0x00fc0000,
 226         .reset_pd = 0xff000000,
 227     }, {
 228         .regs_addr = 0xf0014000,
 229         .reset_pu = 0xffffffff,
 230     }, {
 231         .regs_addr = 0xf0015000,
 232         .reset_pu = 0xbf83f801,
 233         .reset_pd = 0x007c0000,
 234         .reset_osrc = 0x000000f1,
 235         .reset_odsc = 0x3f9f80f1,
 236     }, {
 237         .regs_addr = 0xf0016000,
 238         .reset_pu = 0xfc00f801,
 239         .reset_pd = 0x000007fe,
 240         .reset_odsc = 0x00000800,
 241     }, {
 242         .regs_addr = 0xf0017000,
 243         .unconnected_pins = 0xffffff00,
 244         .reset_pu = 0x0000007f,
 245         .reset_osrc = 0x0000007f,
 246         .reset_odsc = 0x0000007f,
 247     },
 248 };
 249
 250 static const struct {
 251     const char *name;
 252     hwaddr regs_addr;
 253     int cs_count;
 254     const hwaddr *flash_addr;
 255 } npcm7xx_fiu[] = {
 256     {
 257         .name = "fiu0",
 258         .regs_addr = 0xfb000000,
 259         .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
 260         .flash_addr = npcm7xx_fiu0_flash_addr,
 261     }, {
 262         .name = "fiu3",
 263         .regs_addr = 0xc0000000,
 264         .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
 265         .flash_addr = npcm7xx_fiu3_flash_addr,
 266     },
 267 };
 268
 269 static void npcm7xx_write_board_setup(ARMCPU *cpu,
 270                                       const struct arm_boot_info *info)
 271 {
 272     uint32_t board_setup[] = {
 273         0xe59f0010,     /* ldr r0, clk_base_addr */
 274         0xe59f1010,     /* ldr r1, pllcon1_value */
 275         0xe5801010,     /* str r1, [r0, #16] */
 276         0xe59f100c,     /* ldr r1, clksel_value */
 277         0xe5801004,     /* str r1, [r0, #4] */
 278         0xe12fff1e,     /* bx lr */
 279         NPCM7XX_CLK_BA,
 280         NPCM7XX_PLLCON1_FIXUP_VAL,
 281         NPCM7XX_CLKSEL_FIXUP_VAL,
 282     };
 283     int i;
 284
 285     for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
 286         board_setup[i] = tswap32(board_setup[i]);
 287     }
 288     rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
 289                        info->board_setup_addr);
 290 }
 291
 292 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
 293                                          const struct arm_boot_info *info)
 294 {
 295     /*
 296      * The default smpboot stub halts the secondary CPU with a 'wfi'
 297      * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
 298      * does not send an IPI to wake it up, so the second CPU fails to boot. So
 299      * we need to provide our own smpboot stub that can not use 'wfi', it has
 300      * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
 301      */
 302     uint32_t smpboot[] = {
 303         0xe59f2018,     /* ldr r2, bootreg_addr */
 304         0xe3a00000,     /* mov r0, #0 */
 305         0xe5820000,     /* str r0, [r2] */
 306         0xe320f002,     /* wfe */
 307         0xe5921000,     /* ldr r1, [r2] */
 308         0xe1110001,     /* tst r1, r1 */
 309         0x0afffffb,     /* beq <wfe> */
 310         0xe12fff11,     /* bx r1 */
 311         NPCM7XX_SMP_BOOTREG_ADDR,
 312     };
 313     int i;
 314
 315     for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
 316         smpboot[i] = tswap32(smpboot[i]);
 317     }
 318
 319     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
 320                        NPCM7XX_SMP_LOADER_START);
 321 }
 322
 323 static struct arm_boot_info npcm7xx_binfo = {
 324     .loader_start           = NPCM7XX_LOADER_START,
 325     .smp_loader_start       = NPCM7XX_SMP_LOADER_START,
 326     .smp_bootreg_addr       = NPCM7XX_SMP_BOOTREG_ADDR,
 327     .gic_cpu_if_addr        = NPCM7XX_GIC_CPU_IF_ADDR,
 328     .write_secondary_boot   = npcm7xx_write_secondary_boot,
 329     .board_id               = -1,
 330     .board_setup_addr       = NPCM7XX_BOARD_SETUP_ADDR,
 331     .write_board_setup      = npcm7xx_write_board_setup,
 332 };
 333
 334 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
 335 {
 336     NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
 337
 338     npcm7xx_binfo.ram_size = machine->ram_size;
 339     npcm7xx_binfo.nb_cpus = sc->num_cpus;
 340
 341     arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
 342 }
 343
 344 static void npcm7xx_init_fuses(NPCM7xxState *s)
 345 {
 346     NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
 347     uint32_t value;
 348
 349     /*
 350      * The initial mask of disabled modules indicates the chip derivative (e.g.
 351      * NPCM750 or NPCM730).
 352      */
 353     value = tswap32(nc->disabled_modules);
 354     npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
 355                             sizeof(value));
 356 }
 357
 358 static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
 359 {
 360     /* Both ADC and the fuse array must have realized. */
 361     QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
 362     npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
 363             NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
 364 }
 365
 366 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
 367 {
 368     return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
 369 }
 370
 371 static void npcm7xx_init(Object *obj)
 372 {
 373     NPCM7xxState *s = NPCM7XX(obj);
 374     int i;
 375
 376     for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
 377         object_initialize_child(obj, "cpu[*]", &s->cpu[i],
 378                                 ARM_CPU_TYPE_NAME("cortex-a9"));
 379     }
 380
 381     object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
 382     object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
 383     object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
 384                               "power-on-straps");
 385     object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
 386     object_initialize_child(obj, "otp1", &s->key_storage,
 387                             TYPE_NPCM7XX_KEY_STORAGE);
 388     object_initialize_child(obj, "otp2", &s->fuse_array,
 389                             TYPE_NPCM7XX_FUSE_ARRAY);
 390     object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
 391     object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
 392     object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
 393
 394     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
 395         object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
 396     }
 397
 398     for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
 399         object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
 400     }
 401
 402     for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
 403         object_initialize_child(obj, "smbus[*]", &s->smbus[i],
 404                                 TYPE_NPCM7XX_SMBUS);
 405     }
 406
 407     object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
 408     object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
 409
 410     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
 411     for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
 412         object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
 413                                 TYPE_NPCM7XX_FIU);
 414     }
 415
 416     for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 417         object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
 418     }
 419
 420     for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
 421         object_initialize_child(obj, "emc[*]", &s->emc[i], TYPE_NPCM7XX_EMC);
 422     }
 423 }
 424
 425 static void npcm7xx_realize(DeviceState *dev, Error **errp)
 426 {
 427     NPCM7xxState *s = NPCM7XX(dev);
 428     NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
 429     int i;
 430
 431     if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
 432         error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
 433                    " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
 434         return;
 435     }
 436
 437     /* CPUs */
 438     for (i = 0; i < nc->num_cpus; i++) {
 439         object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
 440                                 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
 441                                 &error_abort);
 442         object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
 443                                 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
 444         object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
 445                                  &error_abort);
 446
 447         /* Disable security extensions. */
 448         object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
 449                                  &error_abort);
 450
 451         if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
 452             return;
 453         }
 454     }
 455
 456     /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
 457     object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
 458                             &error_abort);
 459     object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
 460                             &error_abort);
 461     sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
 462     sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
 463
 464     for (i = 0; i < nc->num_cpus; i++) {
 465         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
 466                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
 467         sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
 468                            qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
 469     }
 470
 471     /* L2 cache controller */
 472     sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
 473
 474     /* System Global Control Registers (GCR). Can fail due to user input. */
 475     object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
 476                             nc->disabled_modules, &error_abort);
 477     object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
 478     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
 479         return;
 480     }
 481     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
 482
 483     /* Clock Control Registers (CLK). Cannot fail. */
 484     sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
 485     sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
 486
 487     /* OTP key storage and fuse strap array. Cannot fail. */
 488     sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
 489     sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
 490     sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
 491     sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
 492     npcm7xx_init_fuses(s);
 493
 494     /* Fake Memory Controller (MC). Cannot fail. */
 495     sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
 496     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
 497
 498     /* ADC Modules. Cannot fail. */
 499     qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
 500                           DEVICE(&s->clk), "adc-clock"));
 501     sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
 502     sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
 503     sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
 504             npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
 505     npcm7xx_write_adc_calibration(s);
 506
 507     /* Timer Modules (TIM). Cannot fail. */
 508     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
 509     for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
 510         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
 511         int first_irq;
 512         int j;
 513
 514         /* Connect the timer clock. */
 515         qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
 516                     DEVICE(&s->clk), "timer-clock"));
 517
 518         sysbus_realize(sbd, &error_abort);
 519         sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
 520
 521         first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
 522         for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
 523             qemu_irq irq = npcm7xx_irq(s, first_irq + j);
 524             sysbus_connect_irq(sbd, j, irq);
 525         }
 526
 527         /* IRQ for watchdogs */
 528         sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
 529                 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
 530         /* GPIO that connects clk module with watchdog */
 531         qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
 532                 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
 533                 qdev_get_gpio_in_named(DEVICE(&s->clk),
 534                         NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
 535     }
 536
 537     /* UART0..3 (16550 compatible) */
 538     for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
 539         serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
 540                        npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
 541                        serial_hd(i), DEVICE_LITTLE_ENDIAN);
 542     }
 543
 544     /* Random Number Generator. Cannot fail. */
 545     sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
 546     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
 547
 548     /* GPIO modules. Cannot fail. */
 549     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
 550     for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
 551         Object *obj = OBJECT(&s->gpio[i]);
 552
 553         object_property_set_uint(obj, "reset-pullup",
 554                                  npcm7xx_gpio[i].reset_pu, &error_abort);
 555         object_property_set_uint(obj, "reset-pulldown",
 556                                  npcm7xx_gpio[i].reset_pd, &error_abort);
 557         object_property_set_uint(obj, "reset-osrc",
 558                                  npcm7xx_gpio[i].reset_osrc, &error_abort);
 559         object_property_set_uint(obj, "reset-odsc",
 560                                  npcm7xx_gpio[i].reset_odsc, &error_abort);
 561         sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
 562         sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
 563         sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
 564                            npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
 565     }
 566
 567     /* SMBus modules. Cannot fail. */
 568     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_smbus_addr) != ARRAY_SIZE(s->smbus));
 569     for (i = 0; i < ARRAY_SIZE(s->smbus); i++) {
 570         Object *obj = OBJECT(&s->smbus[i]);
 571
 572         sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
 573         sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_smbus_addr[i]);
 574         sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
 575                            npcm7xx_irq(s, NPCM7XX_SMBUS0_IRQ + i));
 576     }
 577
 578     /* USB Host */
 579     object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
 580                              &error_abort);
 581     sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
 582     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
 583     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
 584                        npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
 585
 586     object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
 587                             &error_abort);
 588     object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
 589     sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
 590     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
 591     sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
 592                        npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
 593
 594     /* PWM Modules. Cannot fail. */
 595     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
 596     for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
 597         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
 598
 599         qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
 600                     DEVICE(&s->clk), "apb3-clock"));
 601         sysbus_realize(sbd, &error_abort);
 602         sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
 603         sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
 604     }
 605
 606     /*
 607      * EMC Modules. Cannot fail.
 608      * The mapping of the device to its netdev backend works as follows:
 609      * emc[i] = nd_table[i]
 610      * This works around the inability to specify the netdev property for the
 611      * emc device: it's not pluggable and thus the -device option can't be
 612      * used.
 613      */
 614     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_emc_addr) != ARRAY_SIZE(s->emc));
 615     QEMU_BUILD_BUG_ON(ARRAY_SIZE(s->emc) != 2);
 616     for (i = 0; i < ARRAY_SIZE(s->emc); i++) {
 617         s->emc[i].emc_num = i;
 618         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->emc[i]);
 619         if (nd_table[i].used) {
 620             qemu_check_nic_model(&nd_table[i], TYPE_NPCM7XX_EMC);
 621             qdev_set_nic_properties(DEVICE(sbd), &nd_table[i]);
 622         }
 623         /*
 624          * The device exists regardless of whether it's connected to a QEMU
 625          * netdev backend. So always instantiate it even if there is no
 626          * backend.
 627          */
 628         sysbus_realize(sbd, &error_abort);
 629         sysbus_mmio_map(sbd, 0, npcm7xx_emc_addr[i]);
 630         int tx_irq = i == 0 ? NPCM7XX_EMC1TX_IRQ : NPCM7XX_EMC2TX_IRQ;
 631         int rx_irq = i == 0 ? NPCM7XX_EMC1RX_IRQ : NPCM7XX_EMC2RX_IRQ;
 632         /*
 633          * N.B. The values for the second argument sysbus_connect_irq are
 634          * chosen to match the registration order in npcm7xx_emc_realize.
 635          */
 636         sysbus_connect_irq(sbd, 0, npcm7xx_irq(s, tx_irq));
 637         sysbus_connect_irq(sbd, 1, npcm7xx_irq(s, rx_irq));
 638     }
 639
 640     /*
 641      * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
 642      * specified, but this is a programming error.
 643      */
 644     QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
 645     for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
 646         SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
 647         int j;
 648
 649         object_property_set_int(OBJECT(sbd), "cs-count",
 650                                 npcm7xx_fiu[i].cs_count, &error_abort);
 651         sysbus_realize(sbd, &error_abort);
 652
 653         sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
 654         for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
 655             sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
 656         }
 657     }
 658
 659     /* RAM2 (SRAM) */
 660     memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
 661                            NPCM7XX_RAM2_SZ, &error_abort);
 662     memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
 663
 664     /* RAM3 (SRAM) */
 665     memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
 666                            NPCM7XX_RAM3_SZ, &error_abort);
 667     memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
 668
 669     /* Internal ROM */
 670     memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
 671                            &error_abort);
 672     memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
 673
 674     create_unimplemented_device("npcm7xx.shm",          0xc0001000,   4 * KiB);
 675     create_unimplemented_device("npcm7xx.vdmx",         0xe0800000,   4 * KiB);
 676     create_unimplemented_device("npcm7xx.pcierc",       0xe1000000,  64 * KiB);
 677     create_unimplemented_device("npcm7xx.kcs",          0xf0007000,   4 * KiB);
 678     create_unimplemented_device("npcm7xx.gfxi",         0xf000e000,   4 * KiB);
 679     create_unimplemented_device("npcm7xx.espi",         0xf009f000,   4 * KiB);
 680     create_unimplemented_device("npcm7xx.peci",         0xf0100000,   4 * KiB);
 681     create_unimplemented_device("npcm7xx.siox[1]",      0xf0101000,   4 * KiB);
 682     create_unimplemented_device("npcm7xx.siox[2]",      0xf0102000,   4 * KiB);
 683     create_unimplemented_device("npcm7xx.mft[0]",       0xf0180000,   4 * KiB);
 684     create_unimplemented_device("npcm7xx.mft[1]",       0xf0181000,   4 * KiB);
 685     create_unimplemented_device("npcm7xx.mft[2]",       0xf0182000,   4 * KiB);
 686     create_unimplemented_device("npcm7xx.mft[3]",       0xf0183000,   4 * KiB);
 687     create_unimplemented_device("npcm7xx.mft[4]",       0xf0184000,   4 * KiB);
 688     create_unimplemented_device("npcm7xx.mft[5]",       0xf0185000,   4 * KiB);
 689     create_unimplemented_device("npcm7xx.mft[6]",       0xf0186000,   4 * KiB);
 690     create_unimplemented_device("npcm7xx.mft[7]",       0xf0187000,   4 * KiB);
 691     create_unimplemented_device("npcm7xx.pspi1",        0xf0200000,   4 * KiB);
 692     create_unimplemented_device("npcm7xx.pspi2",        0xf0201000,   4 * KiB);
 693     create_unimplemented_device("npcm7xx.ahbpci",       0xf0400000,   1 * MiB);
 694     create_unimplemented_device("npcm7xx.mcphy",        0xf05f0000,  64 * KiB);
 695     create_unimplemented_device("npcm7xx.gmac1",        0xf0802000,   8 * KiB);
 696     create_unimplemented_device("npcm7xx.gmac2",        0xf0804000,   8 * KiB);
 697     create_unimplemented_device("npcm7xx.vcd",          0xf0810000,  64 * KiB);
 698     create_unimplemented_device("npcm7xx.ece",          0xf0820000,   8 * KiB);
 699     create_unimplemented_device("npcm7xx.vdma",         0xf0822000,   8 * KiB);
 700     create_unimplemented_device("npcm7xx.usbd[0]",      0xf0830000,   4 * KiB);
 701     create_unimplemented_device("npcm7xx.usbd[1]",      0xf0831000,   4 * KiB);
 702     create_unimplemented_device("npcm7xx.usbd[2]",      0xf0832000,   4 * KiB);
 703     create_unimplemented_device("npcm7xx.usbd[3]",      0xf0833000,   4 * KiB);
 704     create_unimplemented_device("npcm7xx.usbd[4]",      0xf0834000,   4 * KiB);
 705     create_unimplemented_device("npcm7xx.usbd[5]",      0xf0835000,   4 * KiB);
 706     create_unimplemented_device("npcm7xx.usbd[6]",      0xf0836000,   4 * KiB);
 707     create_unimplemented_device("npcm7xx.usbd[7]",      0xf0837000,   4 * KiB);
 708     create_unimplemented_device("npcm7xx.usbd[8]",      0xf0838000,   4 * KiB);
 709     create_unimplemented_device("npcm7xx.usbd[9]",      0xf0839000,   4 * KiB);
 710     create_unimplemented_device("npcm7xx.sd",           0xf0840000,   8 * KiB);
 711     create_unimplemented_device("npcm7xx.mmc",          0xf0842000,   8 * KiB);
 712     create_unimplemented_device("npcm7xx.pcimbx",       0xf0848000, 512 * KiB);
 713     create_unimplemented_device("npcm7xx.aes",          0xf0858000,   4 * KiB);
 714     create_unimplemented_device("npcm7xx.des",          0xf0859000,   4 * KiB);
 715     create_unimplemented_device("npcm7xx.sha",          0xf085a000,   4 * KiB);
 716     create_unimplemented_device("npcm7xx.secacc",       0xf085b000,   4 * KiB);
 717     create_unimplemented_device("npcm7xx.spixcs0",      0xf8000000,  16 * MiB);
 718     create_unimplemented_device("npcm7xx.spixcs1",      0xf9000000,  16 * MiB);
 719     create_unimplemented_device("npcm7xx.spix",         0xfb001000,   4 * KiB);
 720 }
 721
 722 static Property npcm7xx_properties[] = {
 723     DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
 724                      MemoryRegion *),
 725     DEFINE_PROP_END_OF_LIST(),
 726 };
 727
 728 static void npcm7xx_class_init(ObjectClass *oc, void *data)
 729 {
 730     DeviceClass *dc = DEVICE_CLASS(oc);
 731
 732     dc->realize = npcm7xx_realize;
 733     dc->user_creatable = false;
 734     device_class_set_props(dc, npcm7xx_properties);
 735 }
 736
 737 static void npcm730_class_init(ObjectClass *oc, void *data)
 738 {
 739     NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
 740
 741     /* NPCM730 is optimized for data center use, so no graphics, etc. */
 742     nc->disabled_modules = 0x00300395;
 743     nc->num_cpus = 2;
 744 }
 745
 746 static void npcm750_class_init(ObjectClass *oc, void *data)
 747 {
 748     NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
 749
 750     /* NPCM750 has 2 cores and a full set of peripherals */
 751     nc->disabled_modules = 0x00000000;
 752     nc->num_cpus = 2;
 753 }
 754
 755 static const TypeInfo npcm7xx_soc_types[] = {
 756     {
 757         .name           = TYPE_NPCM7XX,
 758         .parent         = TYPE_DEVICE,
 759         .instance_size  = sizeof(NPCM7xxState),
 760         .instance_init  = npcm7xx_init,
 761         .class_size     = sizeof(NPCM7xxClass),
 762         .class_init     = npcm7xx_class_init,
 763         .abstract       = true,
 764     }, {
 765         .name           = TYPE_NPCM730,
 766         .parent         = TYPE_NPCM7XX,
 767         .class_init     = npcm730_class_init,
 768     }, {
 769         .name           = TYPE_NPCM750,
 770         .parent         = TYPE_NPCM7XX,
 771         .class_init     = npcm750_class_init,
 772     },
 773 };
 774
 775 DEFINE_TYPES(npcm7xx_soc_types);