target/mips: Remove XBurst Media eXtension Unit dead code
[qemu/ar7.git] / hw / arm / allwinner-h3.c
blob88259a9c0d1f9dfe2ba60794a1570450f1fa73f4
1 /*
2  * Allwinner H3 System on Chip emulation
3  *
4  * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5  *
6  * This program is free software: you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation, either version 2 of the License, or
9  * (at your option) any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
20 #include "qemu/osdep.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "cpu.h"
28 #include "hw/sysbus.h"
29 #include "hw/char/serial.h"
30 #include "hw/misc/unimp.h"
31 #include "hw/usb/hcd-ehci.h"
32 #include "hw/loader.h"
33 #include "sysemu/sysemu.h"
34 #include "hw/arm/allwinner-h3.h"
36 /* Memory map */
37 const hwaddr allwinner_h3_memmap[] = {
38     [AW_H3_DEV_SRAM_A1]    = 0x00000000,
39     [AW_H3_DEV_SRAM_A2]    = 0x00044000,
40     [AW_H3_DEV_SRAM_C]     = 0x00010000,
41     [AW_H3_DEV_SYSCTRL]    = 0x01c00000,
42     [AW_H3_DEV_MMC0]       = 0x01c0f000,
43     [AW_H3_DEV_SID]        = 0x01c14000,
44     [AW_H3_DEV_EHCI0]      = 0x01c1a000,
45     [AW_H3_DEV_OHCI0]      = 0x01c1a400,
46     [AW_H3_DEV_EHCI1]      = 0x01c1b000,
47     [AW_H3_DEV_OHCI1]      = 0x01c1b400,
48     [AW_H3_DEV_EHCI2]      = 0x01c1c000,
49     [AW_H3_DEV_OHCI2]      = 0x01c1c400,
50     [AW_H3_DEV_EHCI3]      = 0x01c1d000,
51     [AW_H3_DEV_OHCI3]      = 0x01c1d400,
52     [AW_H3_DEV_CCU]        = 0x01c20000,
53     [AW_H3_DEV_PIT]        = 0x01c20c00,
54     [AW_H3_DEV_UART0]      = 0x01c28000,
55     [AW_H3_DEV_UART1]      = 0x01c28400,
56     [AW_H3_DEV_UART2]      = 0x01c28800,
57     [AW_H3_DEV_UART3]      = 0x01c28c00,
58     [AW_H3_DEV_EMAC]       = 0x01c30000,
59     [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
60     [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
61     [AW_H3_DEV_DRAMPHY]    = 0x01c65000,
62     [AW_H3_DEV_GIC_DIST]   = 0x01c81000,
63     [AW_H3_DEV_GIC_CPU]    = 0x01c82000,
64     [AW_H3_DEV_GIC_HYP]    = 0x01c84000,
65     [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
66     [AW_H3_DEV_RTC]        = 0x01f00000,
67     [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
68     [AW_H3_DEV_SDRAM]      = 0x40000000
71 /* List of unimplemented devices */
72 struct AwH3Unimplemented {
73     const char *device_name;
74     hwaddr base;
75     hwaddr size;
76 } unimplemented[] = {
77     { "d-engine",  0x01000000, 4 * MiB },
78     { "d-inter",   0x01400000, 128 * KiB },
79     { "dma",       0x01c02000, 4 * KiB },
80     { "nfdc",      0x01c03000, 4 * KiB },
81     { "ts",        0x01c06000, 4 * KiB },
82     { "keymem",    0x01c0b000, 4 * KiB },
83     { "lcd0",      0x01c0c000, 4 * KiB },
84     { "lcd1",      0x01c0d000, 4 * KiB },
85     { "ve",        0x01c0e000, 4 * KiB },
86     { "mmc1",      0x01c10000, 4 * KiB },
87     { "mmc2",      0x01c11000, 4 * KiB },
88     { "crypto",    0x01c15000, 4 * KiB },
89     { "msgbox",    0x01c17000, 4 * KiB },
90     { "spinlock",  0x01c18000, 4 * KiB },
91     { "usb0-otg",  0x01c19000, 4 * KiB },
92     { "usb0-phy",  0x01c1a000, 4 * KiB },
93     { "usb1-phy",  0x01c1b000, 4 * KiB },
94     { "usb2-phy",  0x01c1c000, 4 * KiB },
95     { "usb3-phy",  0x01c1d000, 4 * KiB },
96     { "smc",       0x01c1e000, 4 * KiB },
97     { "pio",       0x01c20800, 1 * KiB },
98     { "owa",       0x01c21000, 1 * KiB },
99     { "pwm",       0x01c21400, 1 * KiB },
100     { "keyadc",    0x01c21800, 1 * KiB },
101     { "pcm0",      0x01c22000, 1 * KiB },
102     { "pcm1",      0x01c22400, 1 * KiB },
103     { "pcm2",      0x01c22800, 1 * KiB },
104     { "audio",     0x01c22c00, 2 * KiB },
105     { "smta",      0x01c23400, 1 * KiB },
106     { "ths",       0x01c25000, 1 * KiB },
107     { "uart0",     0x01c28000, 1 * KiB },
108     { "uart1",     0x01c28400, 1 * KiB },
109     { "uart2",     0x01c28800, 1 * KiB },
110     { "uart3",     0x01c28c00, 1 * KiB },
111     { "twi0",      0x01c2ac00, 1 * KiB },
112     { "twi1",      0x01c2b000, 1 * KiB },
113     { "twi2",      0x01c2b400, 1 * KiB },
114     { "scr",       0x01c2c400, 1 * KiB },
115     { "gpu",       0x01c40000, 64 * KiB },
116     { "hstmr",     0x01c60000, 4 * KiB },
117     { "spi0",      0x01c68000, 4 * KiB },
118     { "spi1",      0x01c69000, 4 * KiB },
119     { "csi",       0x01cb0000, 320 * KiB },
120     { "tve",       0x01e00000, 64 * KiB },
121     { "hdmi",      0x01ee0000, 128 * KiB },
122     { "r_timer",   0x01f00800, 1 * KiB },
123     { "r_intc",    0x01f00c00, 1 * KiB },
124     { "r_wdog",    0x01f01000, 1 * KiB },
125     { "r_prcm",    0x01f01400, 1 * KiB },
126     { "r_twd",     0x01f01800, 1 * KiB },
127     { "r_cir-rx",  0x01f02000, 1 * KiB },
128     { "r_twi",     0x01f02400, 1 * KiB },
129     { "r_uart",    0x01f02800, 1 * KiB },
130     { "r_pio",     0x01f02c00, 1 * KiB },
131     { "r_pwm",     0x01f03800, 1 * KiB },
132     { "core-dbg",  0x3f500000, 128 * KiB },
133     { "tsgen-ro",  0x3f506000, 4 * KiB },
134     { "tsgen-ctl", 0x3f507000, 4 * KiB },
135     { "ddr-mem",   0x40000000, 2 * GiB },
136     { "n-brom",    0xffff0000, 32 * KiB },
137     { "s-brom",    0xffff0000, 64 * KiB }
140 /* Per Processor Interrupts */
141 enum {
142     AW_H3_GIC_PPI_MAINT     =  9,
143     AW_H3_GIC_PPI_HYPTIMER  = 10,
144     AW_H3_GIC_PPI_VIRTTIMER = 11,
145     AW_H3_GIC_PPI_SECTIMER  = 13,
146     AW_H3_GIC_PPI_PHYSTIMER = 14
149 /* Shared Processor Interrupts */
150 enum {
151     AW_H3_GIC_SPI_UART0     =  0,
152     AW_H3_GIC_SPI_UART1     =  1,
153     AW_H3_GIC_SPI_UART2     =  2,
154     AW_H3_GIC_SPI_UART3     =  3,
155     AW_H3_GIC_SPI_TIMER0    = 18,
156     AW_H3_GIC_SPI_TIMER1    = 19,
157     AW_H3_GIC_SPI_MMC0      = 60,
158     AW_H3_GIC_SPI_EHCI0     = 72,
159     AW_H3_GIC_SPI_OHCI0     = 73,
160     AW_H3_GIC_SPI_EHCI1     = 74,
161     AW_H3_GIC_SPI_OHCI1     = 75,
162     AW_H3_GIC_SPI_EHCI2     = 76,
163     AW_H3_GIC_SPI_OHCI2     = 77,
164     AW_H3_GIC_SPI_EHCI3     = 78,
165     AW_H3_GIC_SPI_OHCI3     = 79,
166     AW_H3_GIC_SPI_EMAC      = 82
169 /* Allwinner H3 general constants */
170 enum {
171     AW_H3_GIC_NUM_SPI       = 128
174 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
176     const int64_t rom_size = 32 * KiB;
177     g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
179     if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
180         error_setg(&error_fatal, "%s: failed to read BlockBackend data",
181                    __func__);
182         return;
183     }
185     rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
186                   rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
187                   NULL, NULL, NULL, NULL, false);
190 static void allwinner_h3_init(Object *obj)
192     AwH3State *s = AW_H3(obj);
194     s->memmap = allwinner_h3_memmap;
196     for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
197         object_initialize_child(obj, "cpu[*]", &s->cpus[i],
198                                 ARM_CPU_TYPE_NAME("cortex-a7"));
199     }
201     object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
203     object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
204     object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
205                               "clk0-freq");
206     object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
207                               "clk1-freq");
209     object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
211     object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
213     object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
215     object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
216     object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
217                               "identifier");
219     object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
221     object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
223     object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
224     object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
225                              "ram-addr");
226     object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
227                               "ram-size");
229     object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
232 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
234     AwH3State *s = AW_H3(dev);
235     unsigned i;
237     /* CPUs */
238     for (i = 0; i < AW_H3_NUM_CPUS; i++) {
240         /* Provide Power State Coordination Interface */
241         qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
242                             QEMU_PSCI_CONDUIT_HVC);
244         /* Disable secondary CPUs */
245         qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
246                           i > 0);
248         /* All exception levels required */
249         qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
250         qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
252         /* Mark realized */
253         qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
254     }
256     /* Generic Interrupt Controller */
257     qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
258                                                      GIC_INTERNAL);
259     qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
260     qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
261     qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
262     qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
263     sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
265     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
266     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
267     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
268     sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
270     /*
271      * Wire the outputs from each CPU's generic timer and the GICv3
272      * maintenance interrupt signal to the appropriate GIC PPI inputs,
273      * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
274      */
275     for (i = 0; i < AW_H3_NUM_CPUS; i++) {
276         DeviceState *cpudev = DEVICE(&s->cpus[i]);
277         int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
278         int irq;
279         /*
280          * Mapping from the output timer irq lines from the CPU to the
281          * GIC PPI inputs used for this board.
282          */
283         const int timer_irq[] = {
284             [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
285             [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
286             [GTIMER_HYP]  = AW_H3_GIC_PPI_HYPTIMER,
287             [GTIMER_SEC]  = AW_H3_GIC_PPI_SECTIMER,
288         };
290         /* Connect CPU timer outputs to GIC PPI inputs */
291         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
292             qdev_connect_gpio_out(cpudev, irq,
293                                   qdev_get_gpio_in(DEVICE(&s->gic),
294                                                    ppibase + timer_irq[irq]));
295         }
297         /* Connect GIC outputs to CPU interrupt inputs */
298         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
299                            qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
300         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
301                            qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
302         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
303                            qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
304         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
305                            qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
307         /* GIC maintenance signal */
308         sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
309                            qdev_get_gpio_in(DEVICE(&s->gic),
310                                             ppibase + AW_H3_GIC_PPI_MAINT));
311     }
313     /* Timer */
314     sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
315     sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
316     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
317                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
318     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
319                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
321     /* SRAM */
322     memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
323                             64 * KiB, &error_abort);
324     memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
325                             32 * KiB, &error_abort);
326     memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
327                             44 * KiB, &error_abort);
328     memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
329                                 &s->sram_a1);
330     memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
331                                 &s->sram_a2);
332     memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
333                                 &s->sram_c);
335     /* Clock Control Unit */
336     sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
337     sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
339     /* System Control */
340     sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
341     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
343     /* CPU Configuration */
344     sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
345     sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
347     /* Security Identifier */
348     sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
349     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
351     /* SD/MMC */
352     object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
353                              OBJECT(get_system_memory()), &error_fatal);
354     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
355     sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
356     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
357                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
359     object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
360                               "sd-bus");
362     /* EMAC */
363     /* FIXME use qdev NIC properties instead of nd_table[] */
364     if (nd_table[0].used) {
365         qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
366         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
367     }
368     object_property_set_link(OBJECT(&s->emac), "dma-memory",
369                              OBJECT(get_system_memory()), &error_fatal);
370     sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
371     sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
372     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
373                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
375     /* Universal Serial Bus */
376     sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
377                          qdev_get_gpio_in(DEVICE(&s->gic),
378                                           AW_H3_GIC_SPI_EHCI0));
379     sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
380                          qdev_get_gpio_in(DEVICE(&s->gic),
381                                           AW_H3_GIC_SPI_EHCI1));
382     sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
383                          qdev_get_gpio_in(DEVICE(&s->gic),
384                                           AW_H3_GIC_SPI_EHCI2));
385     sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
386                          qdev_get_gpio_in(DEVICE(&s->gic),
387                                           AW_H3_GIC_SPI_EHCI3));
389     sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
390                          qdev_get_gpio_in(DEVICE(&s->gic),
391                                           AW_H3_GIC_SPI_OHCI0));
392     sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
393                          qdev_get_gpio_in(DEVICE(&s->gic),
394                                           AW_H3_GIC_SPI_OHCI1));
395     sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
396                          qdev_get_gpio_in(DEVICE(&s->gic),
397                                           AW_H3_GIC_SPI_OHCI2));
398     sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
399                          qdev_get_gpio_in(DEVICE(&s->gic),
400                                           AW_H3_GIC_SPI_OHCI3));
402     /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
403     serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
404                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
405                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
406     /* UART1 */
407     serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
408                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
409                    115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
410     /* UART2 */
411     serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
412                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
413                    115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
414     /* UART3 */
415     serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
416                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
417                    115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
419     /* DRAMC */
420     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
421     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
422     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
423     sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
425     /* RTC */
426     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
427     sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
429     /* Unimplemented devices */
430     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
431         create_unimplemented_device(unimplemented[i].device_name,
432                                     unimplemented[i].base,
433                                     unimplemented[i].size);
434     }
437 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
439     DeviceClass *dc = DEVICE_CLASS(oc);
441     dc->realize = allwinner_h3_realize;
442     /* Reason: uses serial_hd() in realize function */
443     dc->user_creatable = false;
446 static const TypeInfo allwinner_h3_type_info = {
447     .name = TYPE_AW_H3,
448     .parent = TYPE_DEVICE,
449     .instance_size = sizeof(AwH3State),
450     .instance_init = allwinner_h3_init,
451     .class_init = allwinner_h3_class_init,
454 static void allwinner_h3_register_types(void)
456     type_register_static(&allwinner_h3_type_info);
459 type_init(allwinner_h3_register_types)