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Do not include cpu.h if it's not really necessary
[qemu/ar7.git] / hw / arm / aspeed.c
blob7480533cb7cf0e7b7483ea3d6d94fdbb4c1db436
1 /*
2 * OpenPOWER Palmetto BMC
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #include "qemu/osdep.h"
13 #include "qapi/error.h"
14 #include "exec/address-spaces.h"
15 #include "hw/arm/boot.h"
16 #include "hw/arm/aspeed.h"
17 #include "hw/arm/aspeed_soc.h"
18 #include "hw/i2c/smbus_eeprom.h"
19 #include "hw/misc/pca9552.h"
20 #include "hw/misc/tmp105.h"
21 #include "hw/misc/led.h"
22 #include "hw/qdev-properties.h"
23 #include "sysemu/block-backend.h"
24 #include "hw/loader.h"
25 #include "qemu/error-report.h"
26 #include "qemu/units.h"
27
28 static struct arm_boot_info aspeed_board_binfo = {
29 .board_id = -1, /* device-tree-only board */
30 };
31
32 struct AspeedMachineState {
33 /* Private */
34 MachineState parent_obj;
35 /* Public */
36
37 AspeedSoCState soc;
38 MemoryRegion ram_container;
39 MemoryRegion max_ram;
40 bool mmio_exec;
41 char *fmc_model;
42 char *spi_model;
43 };
44
45 /* Palmetto hardware value: 0x120CE416 */
46 #define PALMETTO_BMC_HW_STRAP1 ( \
47 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
48 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
49 SCU_AST2400_HW_STRAP_ACPI_DIS | \
50 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
51 SCU_HW_STRAP_VGA_CLASS_CODE | \
52 SCU_HW_STRAP_LPC_RESET_PIN | \
53 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
54 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
55 SCU_HW_STRAP_SPI_WIDTH | \
56 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
57 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
58
59 /* TODO: Find the actual hardware value */
60 #define SUPERMICROX11_BMC_HW_STRAP1 ( \
61 SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \
62 SCU_AST2400_HW_STRAP_DRAM_CONFIG(2) | \
63 SCU_AST2400_HW_STRAP_ACPI_DIS | \
64 SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
65 SCU_HW_STRAP_VGA_CLASS_CODE | \
66 SCU_HW_STRAP_LPC_RESET_PIN | \
67 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
68 SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
69 SCU_HW_STRAP_SPI_WIDTH | \
70 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
71 SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
72
73 /* AST2500 evb hardware value: 0xF100C2E6 */
74 #define AST2500_EVB_HW_STRAP1 (( \
75 AST2500_HW_STRAP1_DEFAULTS | \
76 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
77 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
78 SCU_AST2500_HW_STRAP_UART_DEBUG | \
79 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
80 SCU_HW_STRAP_MAC1_RGMII | \
81 SCU_HW_STRAP_MAC0_RGMII) & \
82 ~SCU_HW_STRAP_2ND_BOOT_WDT)
83
84 /* Romulus hardware value: 0xF10AD206 */
85 #define ROMULUS_BMC_HW_STRAP1 ( \
86 AST2500_HW_STRAP1_DEFAULTS | \
87 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
88 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
89 SCU_AST2500_HW_STRAP_UART_DEBUG | \
90 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
91 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
92 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
93
94 /* Sonorapass hardware value: 0xF100D216 */
95 #define SONORAPASS_BMC_HW_STRAP1 ( \
96 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
97 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
98 SCU_AST2500_HW_STRAP_UART_DEBUG | \
99 SCU_AST2500_HW_STRAP_RESERVED28 | \
100 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
101 SCU_HW_STRAP_VGA_CLASS_CODE | \
102 SCU_HW_STRAP_LPC_RESET_PIN | \
103 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
104 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
105 SCU_HW_STRAP_VGA_BIOS_ROM | \
106 SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
107 SCU_AST2500_HW_STRAP_RESERVED1)
108
109 /* Swift hardware value: 0xF11AD206 */
110 #define SWIFT_BMC_HW_STRAP1 ( \
111 AST2500_HW_STRAP1_DEFAULTS | \
112 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
113 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
114 SCU_AST2500_HW_STRAP_UART_DEBUG | \
115 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
116 SCU_H_PLL_BYPASS_EN | \
117 SCU_AST2500_HW_STRAP_ACPI_ENABLE | \
118 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER))
119
120 #define G220A_BMC_HW_STRAP1 ( \
121 SCU_AST2500_HW_STRAP_SPI_AUTOFETCH_ENABLE | \
122 SCU_AST2500_HW_STRAP_GPIO_STRAP_ENABLE | \
123 SCU_AST2500_HW_STRAP_UART_DEBUG | \
124 SCU_AST2500_HW_STRAP_RESERVED28 | \
125 SCU_AST2500_HW_STRAP_DDR4_ENABLE | \
126 SCU_HW_STRAP_2ND_BOOT_WDT | \
127 SCU_HW_STRAP_VGA_CLASS_CODE | \
128 SCU_HW_STRAP_LPC_RESET_PIN | \
129 SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_MASTER) | \
130 SCU_AST2500_HW_STRAP_SET_AXI_AHB_RATIO(AXI_AHB_RATIO_2_1) | \
131 SCU_HW_STRAP_VGA_SIZE_SET(VGA_64M_DRAM) | \
132 SCU_AST2500_HW_STRAP_RESERVED1)
133
134 /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */
135 #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1
136
137 /* AST2600 evb hardware value */
138 #define AST2600_EVB_HW_STRAP1 0x000000C0
139 #define AST2600_EVB_HW_STRAP2 0x00000003
140
141 /* Tacoma hardware value */
142 #define TACOMA_BMC_HW_STRAP1 0x00000000
143 #define TACOMA_BMC_HW_STRAP2 0x00000040
144
145 /*
146 * The max ram region is for firmwares that scan the address space
147 * with load/store to guess how much RAM the SoC has.
148 */
149 static uint64_t max_ram_read(void *opaque, hwaddr offset, unsigned size)
150 {
151 return 0;
152 }
153
154 static void max_ram_write(void *opaque, hwaddr offset, uint64_t value,
155 unsigned size)
156 {
157 /* Discard writes */
158 }
159
160 static const MemoryRegionOps max_ram_ops = {
161 .read = max_ram_read,
162 .write = max_ram_write,
163 .endianness = DEVICE_NATIVE_ENDIAN,
164 };
165
166 #define AST_SMP_MAILBOX_BASE 0x1e6e2180
167 #define AST_SMP_MBOX_FIELD_ENTRY (AST_SMP_MAILBOX_BASE + 0x0)
168 #define AST_SMP_MBOX_FIELD_GOSIGN (AST_SMP_MAILBOX_BASE + 0x4)
169 #define AST_SMP_MBOX_FIELD_READY (AST_SMP_MAILBOX_BASE + 0x8)
170 #define AST_SMP_MBOX_FIELD_POLLINSN (AST_SMP_MAILBOX_BASE + 0xc)
171 #define AST_SMP_MBOX_CODE (AST_SMP_MAILBOX_BASE + 0x10)
172 #define AST_SMP_MBOX_GOSIGN 0xabbaab00
173
174 static void aspeed_write_smpboot(ARMCPU *cpu,
175 const struct arm_boot_info *info)
176 {
177 static const uint32_t poll_mailbox_ready[] = {
178 /*
179 * r2 = per-cpu go sign value
180 * r1 = AST_SMP_MBOX_FIELD_ENTRY
181 * r0 = AST_SMP_MBOX_FIELD_GOSIGN
182 */
183 0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 */
184 0xe21000ff, /* ands r0, r0, #255 */
185 0xe59f201c, /* ldr r2, [pc, #28] */
186 0xe1822000, /* orr r2, r2, r0 */
187
188 0xe59f1018, /* ldr r1, [pc, #24] */
189 0xe59f0018, /* ldr r0, [pc, #24] */
190
191 0xe320f002, /* wfe */
192 0xe5904000, /* ldr r4, [r0] */
193 0xe1520004, /* cmp r2, r4 */
194 0x1afffffb, /* bne <wfe> */
195 0xe591f000, /* ldr pc, [r1] */
196 AST_SMP_MBOX_GOSIGN,
197 AST_SMP_MBOX_FIELD_ENTRY,
198 AST_SMP_MBOX_FIELD_GOSIGN,
199 };
200
201 rom_add_blob_fixed("aspeed.smpboot", poll_mailbox_ready,
202 sizeof(poll_mailbox_ready),
203 info->smp_loader_start);
204 }
205
206 static void aspeed_reset_secondary(ARMCPU *cpu,
207 const struct arm_boot_info *info)
208 {
209 AddressSpace *as = arm_boot_address_space(cpu, info);
210 CPUState *cs = CPU(cpu);
211
212 /* info->smp_bootreg_addr */
213 address_space_stl_notdirty(as, AST_SMP_MBOX_FIELD_GOSIGN, 0,
214 MEMTXATTRS_UNSPECIFIED, NULL);
215 cpu_set_pc(cs, info->smp_loader_start);
216 }
217
218 #define FIRMWARE_ADDR 0x0
219
220 static void write_boot_rom(DriveInfo *dinfo, hwaddr addr, size_t rom_size,
221 Error **errp)
222 {
223 BlockBackend *blk = blk_by_legacy_dinfo(dinfo);
224 uint8_t *storage;
225 int64_t size;
226
227 /* The block backend size should have already been 'validated' by
228 * the creation of the m25p80 object.
229 */
230 size = blk_getlength(blk);
231 if (size <= 0) {
232 error_setg(errp, "failed to get flash size");
233 return;
234 }
235
236 if (rom_size > size) {
237 rom_size = size;
238 }
239
240 storage = g_new0(uint8_t, rom_size);
241 if (blk_pread(blk, 0, storage, rom_size) < 0) {
242 error_setg(errp, "failed to read the initial flash content");
243 return;
244 }
245
246 rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
247 g_free(storage);
248 }
249
250 static void aspeed_board_init_flashes(AspeedSMCState *s,
251 const char *flashtype)
252 {
253 int i ;
254
255 for (i = 0; i < s->num_cs; ++i) {
256 AspeedSMCFlash *fl = &s->flashes[i];
257 DriveInfo *dinfo = drive_get_next(IF_MTD);
258 qemu_irq cs_line;
259
260 fl->flash = qdev_new(flashtype);
261 if (dinfo) {
262 qdev_prop_set_drive(fl->flash, "drive",
263 blk_by_legacy_dinfo(dinfo));
264 }
265 qdev_realize_and_unref(fl->flash, BUS(s->spi), &error_fatal);
266
267 cs_line = qdev_get_gpio_in_named(fl->flash, SSI_GPIO_CS, 0);
268 sysbus_connect_irq(SYS_BUS_DEVICE(s), i + 1, cs_line);
269 }
270 }
271
272 static void sdhci_attach_drive(SDHCIState *sdhci, DriveInfo *dinfo)
273 {
274 DeviceState *card;
275
276 if (!dinfo) {
277 return;
278 }
279 card = qdev_new(TYPE_SD_CARD);
280 qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo),
281 &error_fatal);
282 qdev_realize_and_unref(card,
283 qdev_get_child_bus(DEVICE(sdhci), "sd-bus"),
284 &error_fatal);
285 }
286
287 static void aspeed_machine_init(MachineState *machine)
288 {
289 AspeedMachineState *bmc = ASPEED_MACHINE(machine);
290 AspeedMachineClass *amc = ASPEED_MACHINE_GET_CLASS(machine);
291 AspeedSoCClass *sc;
292 DriveInfo *drive0 = drive_get(IF_MTD, 0, 0);
293 ram_addr_t max_ram_size;
294 int i;
295 NICInfo *nd = &nd_table[0];
296
297 memory_region_init(&bmc->ram_container, NULL, "aspeed-ram-container",
298 4 * GiB);
299 memory_region_add_subregion(&bmc->ram_container, 0, machine->ram);
300
301 object_initialize_child(OBJECT(machine), "soc", &bmc->soc, amc->soc_name);
302
303 sc = ASPEED_SOC_GET_CLASS(&bmc->soc);
304
305 /*
306 * This will error out if isize is not supported by memory controller.
307 */
308 object_property_set_uint(OBJECT(&bmc->soc), "ram-size", machine->ram_size,
309 &error_fatal);
310
311 for (i = 0; i < sc->macs_num; i++) {
312 if ((amc->macs_mask & (1 << i)) && nd->used) {
313 qemu_check_nic_model(nd, TYPE_FTGMAC100);
314 qdev_set_nic_properties(DEVICE(&bmc->soc.ftgmac100[i]), nd);
315 nd++;
316 }
317 }
318
319 object_property_set_int(OBJECT(&bmc->soc), "hw-strap1", amc->hw_strap1,
320 &error_abort);
321 object_property_set_int(OBJECT(&bmc->soc), "hw-strap2", amc->hw_strap2,
322 &error_abort);
323 object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs,
324 &error_abort);
325 object_property_set_link(OBJECT(&bmc->soc), "dram",
326 OBJECT(&bmc->ram_container), &error_abort);
327 if (machine->kernel_filename) {
328 /*
329 * When booting with a -kernel command line there is no u-boot
330 * that runs to unlock the SCU. In this case set the default to
331 * be unlocked as the kernel expects
332 */
333 object_property_set_int(OBJECT(&bmc->soc), "hw-prot-key",
334 ASPEED_SCU_PROT_KEY, &error_abort);
335 }
336 qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort);
337
338 memory_region_add_subregion(get_system_memory(),
339 sc->memmap[ASPEED_DEV_SDRAM],
340 &bmc->ram_container);
341
342 max_ram_size = object_property_get_uint(OBJECT(&bmc->soc), "max-ram-size",
343 &error_abort);
344 memory_region_init_io(&bmc->max_ram, NULL, &max_ram_ops, NULL,
345 "max_ram", max_ram_size - machine->ram_size);
346 memory_region_add_subregion(&bmc->ram_container, machine->ram_size, &bmc->max_ram);
347
348 aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ?
349 bmc->fmc_model : amc->fmc_model);
350 aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ?
351 bmc->spi_model : amc->spi_model);
352
353 /* Install first FMC flash content as a boot rom. */
354 if (drive0) {
355 AspeedSMCFlash *fl = &bmc->soc.fmc.flashes[0];
356 MemoryRegion *boot_rom = g_new(MemoryRegion, 1);
357
358 /*
359 * create a ROM region using the default mapping window size of
360 * the flash module. The window size is 64MB for the AST2400
361 * SoC and 128MB for the AST2500 SoC, which is twice as big as
362 * needed by the flash modules of the Aspeed machines.
363 */
364 if (ASPEED_MACHINE(machine)->mmio_exec) {
365 memory_region_init_alias(boot_rom, NULL, "aspeed.boot_rom",
366 &fl->mmio, 0, fl->size);
367 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
368 boot_rom);
369 } else {
370 memory_region_init_rom(boot_rom, NULL, "aspeed.boot_rom",
371 fl->size, &error_abort);
372 memory_region_add_subregion(get_system_memory(), FIRMWARE_ADDR,
373 boot_rom);
374 write_boot_rom(drive0, FIRMWARE_ADDR, fl->size, &error_abort);
375 }
376 }
377
378 if (machine->kernel_filename && sc->num_cpus > 1) {
379 /* With no u-boot we must set up a boot stub for the secondary CPU */
380 MemoryRegion *smpboot = g_new(MemoryRegion, 1);
381 memory_region_init_ram(smpboot, NULL, "aspeed.smpboot",
382 0x80, &error_abort);
383 memory_region_add_subregion(get_system_memory(),
384 AST_SMP_MAILBOX_BASE, smpboot);
385
386 aspeed_board_binfo.write_secondary_boot = aspeed_write_smpboot;
387 aspeed_board_binfo.secondary_cpu_reset_hook = aspeed_reset_secondary;
388 aspeed_board_binfo.smp_loader_start = AST_SMP_MBOX_CODE;
389 }
390
391 aspeed_board_binfo.ram_size = machine->ram_size;
392 aspeed_board_binfo.loader_start = sc->memmap[ASPEED_DEV_SDRAM];
393 aspeed_board_binfo.nb_cpus = sc->num_cpus;
394
395 if (amc->i2c_init) {
396 amc->i2c_init(bmc);
397 }
398
399 for (i = 0; i < bmc->soc.sdhci.num_slots; i++) {
400 sdhci_attach_drive(&bmc->soc.sdhci.slots[i], drive_get_next(IF_SD));
401 }
402
403 if (bmc->soc.emmc.num_slots) {
404 sdhci_attach_drive(&bmc->soc.emmc.slots[0], drive_get_next(IF_SD));
405 }
406
407 arm_load_kernel(ARM_CPU(first_cpu), machine, &aspeed_board_binfo);
408 }
409
410 static void palmetto_bmc_i2c_init(AspeedMachineState *bmc)
411 {
412 AspeedSoCState *soc = &bmc->soc;
413 DeviceState *dev;
414 uint8_t *eeprom_buf = g_malloc0(32 * 1024);
415
416 /* The palmetto platform expects a ds3231 RTC but a ds1338 is
417 * enough to provide basic RTC features. Alarms will be missing */
418 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 0), "ds1338", 0x68);
419
420 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 0), 0x50,
421 eeprom_buf);
422
423 /* add a TMP423 temperature sensor */
424 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2),
425 "tmp423", 0x4c));
426 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
427 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
428 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
429 object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort);
430 }
431
432 static void ast2500_evb_i2c_init(AspeedMachineState *bmc)
433 {
434 AspeedSoCState *soc = &bmc->soc;
435 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
436
437 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 3), 0x50,
438 eeprom_buf);
439
440 /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */
441 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7),
442 TYPE_TMP105, 0x4d);
443
444 /* The AST2500 EVB does not have an RTC. Let's pretend that one is
445 * plugged on the I2C bus header */
446 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
447 }
448
449 static void ast2600_evb_i2c_init(AspeedMachineState *bmc)
450 {
451 /* Start with some devices on our I2C busses */
452 ast2500_evb_i2c_init(bmc);
453 }
454
455 static void romulus_bmc_i2c_init(AspeedMachineState *bmc)
456 {
457 AspeedSoCState *soc = &bmc->soc;
458
459 /* The romulus board expects Epson RX8900 I2C RTC but a ds1338 is
460 * good enough */
461 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
462 }
463
464 static void swift_bmc_i2c_init(AspeedMachineState *bmc)
465 {
466 AspeedSoCState *soc = &bmc->soc;
467
468 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3), "pca9552", 0x60);
469
470 /* The swift board expects a TMP275 but a TMP105 is compatible */
471 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "tmp105", 0x48);
472 /* The swift board expects a pca9551 but a pca9552 is compatible */
473 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x60);
474
475 /* The swift board expects an Epson RX8900 RTC but a ds1338 is compatible */
476 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "ds1338", 0x32);
477 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
478
479 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c);
480 /* The swift board expects a pca9539 but a pca9552 is compatible */
481 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "pca9552", 0x74);
482
483 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c);
484 /* The swift board expects a pca9539 but a pca9552 is compatible */
485 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "pca9552",
486 0x74);
487
488 /* The swift board expects a TMP275 but a TMP105 is compatible */
489 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x48);
490 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12), "tmp105", 0x4a);
491 }
492
493 static void sonorapass_bmc_i2c_init(AspeedMachineState *bmc)
494 {
495 AspeedSoCState *soc = &bmc->soc;
496
497 /* bus 2 : */
498 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x48);
499 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 2), "tmp105", 0x49);
500 /* bus 2 : pca9546 @ 0x73 */
501
502 /* bus 3 : pca9548 @ 0x70 */
503
504 /* bus 4 : */
505 uint8_t *eeprom4_54 = g_malloc0(8 * 1024);
506 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x54,
507 eeprom4_54);
508 /* PCA9539 @ 0x76, but PCA9552 is compatible */
509 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x76);
510 /* PCA9539 @ 0x77, but PCA9552 is compatible */
511 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "pca9552", 0x77);
512
513 /* bus 6 : */
514 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x48);
515 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), "tmp105", 0x49);
516 /* bus 6 : pca9546 @ 0x73 */
517
518 /* bus 8 : */
519 uint8_t *eeprom8_56 = g_malloc0(8 * 1024);
520 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 8), 0x56,
521 eeprom8_56);
522 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x60);
523 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61);
524 /* bus 8 : adc128d818 @ 0x1d */
525 /* bus 8 : adc128d818 @ 0x1f */
526
527 /*
528 * bus 13 : pca9548 @ 0x71
529 * - channel 3:
530 * - tmm421 @ 0x4c
531 * - tmp421 @ 0x4e
532 * - tmp421 @ 0x4f
533 */
534
535 }
536
537 static void witherspoon_bmc_i2c_init(AspeedMachineState *bmc)
538 {
539 static const struct {
540 unsigned gpio_id;
541 LEDColor color;
542 const char *description;
543 bool gpio_polarity;
544 } pca1_leds[] = {
545 {13, LED_COLOR_GREEN, "front-fault-4", GPIO_POLARITY_ACTIVE_LOW},
546 {14, LED_COLOR_GREEN, "front-power-3", GPIO_POLARITY_ACTIVE_LOW},
547 {15, LED_COLOR_GREEN, "front-id-5", GPIO_POLARITY_ACTIVE_LOW},
548 };
549 AspeedSoCState *soc = &bmc->soc;
550 uint8_t *eeprom_buf = g_malloc0(8 * 1024);
551 DeviceState *dev;
552 LEDState *led;
553
554 /* Bus 3: TODO bmp280@77 */
555 /* Bus 3: TODO max31785@52 */
556 /* Bus 3: TODO dps310@76 */
557 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
558 qdev_prop_set_string(dev, "description", "pca1");
559 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
560 aspeed_i2c_get_bus(&soc->i2c, 3),
561 &error_fatal);
562
563 for (size_t i = 0; i < ARRAY_SIZE(pca1_leds); i++) {
564 led = led_create_simple(OBJECT(bmc),
565 pca1_leds[i].gpio_polarity,
566 pca1_leds[i].color,
567 pca1_leds[i].description);
568 qdev_connect_gpio_out(dev, pca1_leds[i].gpio_id,
569 qdev_get_gpio_in(DEVICE(led), 0));
570 }
571 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), "tmp423", 0x4c);
572 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), "tmp423", 0x4c);
573
574 /* The Witherspoon expects a TMP275 but a TMP105 is compatible */
575 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), TYPE_TMP105,
576 0x4a);
577
578 /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is
579 * good enough */
580 i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), "ds1338", 0x32);
581
582 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 11), 0x51,
583 eeprom_buf);
584 dev = DEVICE(i2c_slave_new(TYPE_PCA9552, 0x60));
585 qdev_prop_set_string(dev, "description", "pca0");
586 i2c_slave_realize_and_unref(I2C_SLAVE(dev),
587 aspeed_i2c_get_bus(&soc->i2c, 11),
588 &error_fatal);
589 /* Bus 11: TODO ucd90160@64 */
590 }
591
592 static void g220a_bmc_i2c_init(AspeedMachineState *bmc)
593 {
594 AspeedSoCState *soc = &bmc->soc;
595 DeviceState *dev;
596
597 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 3),
598 "emc1413", 0x4c));
599 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
600 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
601 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
602
603 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 12),
604 "emc1413", 0x4c));
605 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
606 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
607 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
608
609 dev = DEVICE(i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 13),
610 "emc1413", 0x4c));
611 object_property_set_int(OBJECT(dev), "temperature0", 31000, &error_abort);
612 object_property_set_int(OBJECT(dev), "temperature1", 28000, &error_abort);
613 object_property_set_int(OBJECT(dev), "temperature2", 20000, &error_abort);
614
615 static uint8_t eeprom_buf[2 * 1024] = {
616 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0xfe,
617 0x01, 0x06, 0x00, 0xc9, 0x42, 0x79, 0x74, 0x65,
618 0x64, 0x61, 0x6e, 0x63, 0x65, 0xc5, 0x47, 0x32,
619 0x32, 0x30, 0x41, 0xc4, 0x41, 0x41, 0x42, 0x42,
620 0xc4, 0x43, 0x43, 0x44, 0x44, 0xc4, 0x45, 0x45,
621 0x46, 0x46, 0xc4, 0x48, 0x48, 0x47, 0x47, 0xc1,
622 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xa7,
623 };
624 smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 4), 0x57,
625 eeprom_buf);
626 }
627
628 static bool aspeed_get_mmio_exec(Object *obj, Error **errp)
629 {
630 return ASPEED_MACHINE(obj)->mmio_exec;
631 }
632
633 static void aspeed_set_mmio_exec(Object *obj, bool value, Error **errp)
634 {
635 ASPEED_MACHINE(obj)->mmio_exec = value;
636 }
637
638 static void aspeed_machine_instance_init(Object *obj)
639 {
640 ASPEED_MACHINE(obj)->mmio_exec = false;
641 }
642
643 static char *aspeed_get_fmc_model(Object *obj, Error **errp)
644 {
645 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
646 return g_strdup(bmc->fmc_model);
647 }
648
649 static void aspeed_set_fmc_model(Object *obj, const char *value, Error **errp)
650 {
651 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
652
653 g_free(bmc->fmc_model);
654 bmc->fmc_model = g_strdup(value);
655 }
656
657 static char *aspeed_get_spi_model(Object *obj, Error **errp)
658 {
659 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
660 return g_strdup(bmc->spi_model);
661 }
662
663 static void aspeed_set_spi_model(Object *obj, const char *value, Error **errp)
664 {
665 AspeedMachineState *bmc = ASPEED_MACHINE(obj);
666
667 g_free(bmc->spi_model);
668 bmc->spi_model = g_strdup(value);
669 }
670
671 static void aspeed_machine_class_props_init(ObjectClass *oc)
672 {
673 object_class_property_add_bool(oc, "execute-in-place",
674 aspeed_get_mmio_exec,
675 aspeed_set_mmio_exec);
676 object_class_property_set_description(oc, "execute-in-place",
677 "boot directly from CE0 flash device");
678
679 object_class_property_add_str(oc, "fmc-model", aspeed_get_fmc_model,
680 aspeed_set_fmc_model);
681 object_class_property_set_description(oc, "fmc-model",
682 "Change the FMC Flash model");
683 object_class_property_add_str(oc, "spi-model", aspeed_get_spi_model,
684 aspeed_set_spi_model);
685 object_class_property_set_description(oc, "spi-model",
686 "Change the SPI Flash model");
687 }
688
689 static int aspeed_soc_num_cpus(const char *soc_name)
690 {
691 AspeedSoCClass *sc = ASPEED_SOC_CLASS(object_class_by_name(soc_name));
692 return sc->num_cpus;
693 }
694
695 static void aspeed_machine_class_init(ObjectClass *oc, void *data)
696 {
697 MachineClass *mc = MACHINE_CLASS(oc);
698 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
699
700 mc->init = aspeed_machine_init;
701 mc->no_floppy = 1;
702 mc->no_cdrom = 1;
703 mc->no_parallel = 1;
704 mc->default_ram_id = "ram";
705 amc->macs_mask = ASPEED_MAC0_ON;
706
707 aspeed_machine_class_props_init(oc);
708 }
709
710 static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data)
711 {
712 MachineClass *mc = MACHINE_CLASS(oc);
713 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
714
715 mc->desc = "OpenPOWER Palmetto BMC (ARM926EJ-S)";
716 amc->soc_name = "ast2400-a1";
717 amc->hw_strap1 = PALMETTO_BMC_HW_STRAP1;
718 amc->fmc_model = "n25q256a";
719 amc->spi_model = "mx25l25635e";
720 amc->num_cs = 1;
721 amc->i2c_init = palmetto_bmc_i2c_init;
722 mc->default_ram_size = 256 * MiB;
723 mc->default_cpus = mc->min_cpus = mc->max_cpus =
724 aspeed_soc_num_cpus(amc->soc_name);
725 };
726
727 static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc,
728 void *data)
729 {
730 MachineClass *mc = MACHINE_CLASS(oc);
731 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
732
733 mc->desc = "Supermicro X11 BMC (ARM926EJ-S)";
734 amc->soc_name = "ast2400-a1";
735 amc->hw_strap1 = SUPERMICROX11_BMC_HW_STRAP1;
736 amc->fmc_model = "mx25l25635e";
737 amc->spi_model = "mx25l25635e";
738 amc->num_cs = 1;
739 amc->macs_mask = ASPEED_MAC0_ON | ASPEED_MAC1_ON;
740 amc->i2c_init = palmetto_bmc_i2c_init;
741 mc->default_ram_size = 256 * MiB;
742 }
743
744 static void aspeed_machine_ast2500_evb_class_init(ObjectClass *oc, void *data)
745 {
746 MachineClass *mc = MACHINE_CLASS(oc);
747 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
748
749 mc->desc = "Aspeed AST2500 EVB (ARM1176)";
750 amc->soc_name = "ast2500-a1";
751 amc->hw_strap1 = AST2500_EVB_HW_STRAP1;
752 amc->fmc_model = "w25q256";
753 amc->spi_model = "mx25l25635e";
754 amc->num_cs = 1;
755 amc->i2c_init = ast2500_evb_i2c_init;
756 mc->default_ram_size = 512 * MiB;
757 mc->default_cpus = mc->min_cpus = mc->max_cpus =
758 aspeed_soc_num_cpus(amc->soc_name);
759 };
760
761 static void aspeed_machine_romulus_class_init(ObjectClass *oc, void *data)
762 {
763 MachineClass *mc = MACHINE_CLASS(oc);
764 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
765
766 mc->desc = "OpenPOWER Romulus BMC (ARM1176)";
767 amc->soc_name = "ast2500-a1";
768 amc->hw_strap1 = ROMULUS_BMC_HW_STRAP1;
769 amc->fmc_model = "n25q256a";
770 amc->spi_model = "mx66l1g45g";
771 amc->num_cs = 2;
772 amc->i2c_init = romulus_bmc_i2c_init;
773 mc->default_ram_size = 512 * MiB;
774 mc->default_cpus = mc->min_cpus = mc->max_cpus =
775 aspeed_soc_num_cpus(amc->soc_name);
776 };
777
778 static void aspeed_machine_sonorapass_class_init(ObjectClass *oc, void *data)
779 {
780 MachineClass *mc = MACHINE_CLASS(oc);
781 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
782
783 mc->desc = "OCP SonoraPass BMC (ARM1176)";
784 amc->soc_name = "ast2500-a1";
785 amc->hw_strap1 = SONORAPASS_BMC_HW_STRAP1;
786 amc->fmc_model = "mx66l1g45g";
787 amc->spi_model = "mx66l1g45g";
788 amc->num_cs = 2;
789 amc->i2c_init = sonorapass_bmc_i2c_init;
790 mc->default_ram_size = 512 * MiB;
791 mc->default_cpus = mc->min_cpus = mc->max_cpus =
792 aspeed_soc_num_cpus(amc->soc_name);
793 };
794
795 static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data)
796 {
797 MachineClass *mc = MACHINE_CLASS(oc);
798 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
799
800 mc->desc = "OpenPOWER Swift BMC (ARM1176)";
801 amc->soc_name = "ast2500-a1";
802 amc->hw_strap1 = SWIFT_BMC_HW_STRAP1;
803 amc->fmc_model = "mx66l1g45g";
804 amc->spi_model = "mx66l1g45g";
805 amc->num_cs = 2;
806 amc->i2c_init = swift_bmc_i2c_init;
807 mc->default_ram_size = 512 * MiB;
808 mc->default_cpus = mc->min_cpus = mc->max_cpus =
809 aspeed_soc_num_cpus(amc->soc_name);
810 };
811
812 static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data)
813 {
814 MachineClass *mc = MACHINE_CLASS(oc);
815 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
816
817 mc->desc = "OpenPOWER Witherspoon BMC (ARM1176)";
818 amc->soc_name = "ast2500-a1";
819 amc->hw_strap1 = WITHERSPOON_BMC_HW_STRAP1;
820 amc->fmc_model = "mx25l25635e";
821 amc->spi_model = "mx66l1g45g";
822 amc->num_cs = 2;
823 amc->i2c_init = witherspoon_bmc_i2c_init;
824 mc->default_ram_size = 512 * MiB;
825 mc->default_cpus = mc->min_cpus = mc->max_cpus =
826 aspeed_soc_num_cpus(amc->soc_name);
827 };
828
829 static void aspeed_machine_ast2600_evb_class_init(ObjectClass *oc, void *data)
830 {
831 MachineClass *mc = MACHINE_CLASS(oc);
832 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
833
834 mc->desc = "Aspeed AST2600 EVB (Cortex A7)";
835 amc->soc_name = "ast2600-a1";
836 amc->hw_strap1 = AST2600_EVB_HW_STRAP1;
837 amc->hw_strap2 = AST2600_EVB_HW_STRAP2;
838 amc->fmc_model = "w25q512jv";
839 amc->spi_model = "mx66u51235f";
840 amc->num_cs = 1;
841 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON | ASPEED_MAC3_ON;
842 amc->i2c_init = ast2600_evb_i2c_init;
843 mc->default_ram_size = 1 * GiB;
844 mc->default_cpus = mc->min_cpus = mc->max_cpus =
845 aspeed_soc_num_cpus(amc->soc_name);
846 };
847
848 static void aspeed_machine_tacoma_class_init(ObjectClass *oc, void *data)
849 {
850 MachineClass *mc = MACHINE_CLASS(oc);
851 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
852
853 mc->desc = "OpenPOWER Tacoma BMC (Cortex A7)";
854 amc->soc_name = "ast2600-a1";
855 amc->hw_strap1 = TACOMA_BMC_HW_STRAP1;
856 amc->hw_strap2 = TACOMA_BMC_HW_STRAP2;
857 amc->fmc_model = "mx66l1g45g";
858 amc->spi_model = "mx66l1g45g";
859 amc->num_cs = 2;
860 amc->macs_mask = ASPEED_MAC2_ON;
861 amc->i2c_init = witherspoon_bmc_i2c_init; /* Same board layout */
862 mc->default_ram_size = 1 * GiB;
863 mc->default_cpus = mc->min_cpus = mc->max_cpus =
864 aspeed_soc_num_cpus(amc->soc_name);
865 };
866
867 static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data)
868 {
869 MachineClass *mc = MACHINE_CLASS(oc);
870 AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc);
871
872 mc->desc = "Bytedance G220A BMC (ARM1176)";
873 amc->soc_name = "ast2500-a1";
874 amc->hw_strap1 = G220A_BMC_HW_STRAP1;
875 amc->fmc_model = "n25q512a";
876 amc->spi_model = "mx25l25635e";
877 amc->num_cs = 2;
878 amc->macs_mask = ASPEED_MAC1_ON | ASPEED_MAC2_ON;
879 amc->i2c_init = g220a_bmc_i2c_init;
880 mc->default_ram_size = 1024 * MiB;
881 mc->default_cpus = mc->min_cpus = mc->max_cpus =
882 aspeed_soc_num_cpus(amc->soc_name);
883 };
884
885 static const TypeInfo aspeed_machine_types[] = {
886 {
887 .name = MACHINE_TYPE_NAME("palmetto-bmc"),
888 .parent = TYPE_ASPEED_MACHINE,
889 .class_init = aspeed_machine_palmetto_class_init,
890 }, {
891 .name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
892 .parent = TYPE_ASPEED_MACHINE,
893 .class_init = aspeed_machine_supermicrox11_bmc_class_init,
894 }, {
895 .name = MACHINE_TYPE_NAME("ast2500-evb"),
896 .parent = TYPE_ASPEED_MACHINE,
897 .class_init = aspeed_machine_ast2500_evb_class_init,
898 }, {
899 .name = MACHINE_TYPE_NAME("romulus-bmc"),
900 .parent = TYPE_ASPEED_MACHINE,
901 .class_init = aspeed_machine_romulus_class_init,
902 }, {
903 .name = MACHINE_TYPE_NAME("swift-bmc"),
904 .parent = TYPE_ASPEED_MACHINE,
905 .class_init = aspeed_machine_swift_class_init,
906 }, {
907 .name = MACHINE_TYPE_NAME("sonorapass-bmc"),
908 .parent = TYPE_ASPEED_MACHINE,
909 .class_init = aspeed_machine_sonorapass_class_init,
910 }, {
911 .name = MACHINE_TYPE_NAME("witherspoon-bmc"),
912 .parent = TYPE_ASPEED_MACHINE,
913 .class_init = aspeed_machine_witherspoon_class_init,
914 }, {
915 .name = MACHINE_TYPE_NAME("ast2600-evb"),
916 .parent = TYPE_ASPEED_MACHINE,
917 .class_init = aspeed_machine_ast2600_evb_class_init,
918 }, {
919 .name = MACHINE_TYPE_NAME("tacoma-bmc"),
920 .parent = TYPE_ASPEED_MACHINE,
921 .class_init = aspeed_machine_tacoma_class_init,
922 }, {
923 .name = MACHINE_TYPE_NAME("g220a-bmc"),
924 .parent = TYPE_ASPEED_MACHINE,
925 .class_init = aspeed_machine_g220a_class_init,
926 }, {
927 .name = TYPE_ASPEED_MACHINE,
928 .parent = TYPE_MACHINE,
929 .instance_size = sizeof(AspeedMachineState),
930 .instance_init = aspeed_machine_instance_init,
931 .class_size = sizeof(AspeedMachineClass),
932 .class_init = aspeed_machine_class_init,
933 .abstract = true,
934 }
935 };
936
937 DEFINE_TYPES(aspeed_machine_types)
AR7 emulation for QEMU