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Do not include cpu.h if it's not really necessary
[qemu/ar7.git] / hw / arm / allwinner-h3.c
blobbbe65d1860c65155f125b3001efdc55883ebacc1
1 /*
2 * Allwinner H3 System on Chip emulation
3 *
4 * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "exec/address-spaces.h"
22 #include "qapi/error.h"
23 #include "qemu/error-report.h"
24 #include "qemu/module.h"
25 #include "qemu/units.h"
26 #include "hw/qdev-core.h"
27 #include "hw/sysbus.h"
28 #include "hw/char/serial.h"
29 #include "hw/misc/unimp.h"
30 #include "hw/usb/hcd-ehci.h"
31 #include "hw/loader.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/arm/allwinner-h3.h"
34
35 /* Memory map */
36 const hwaddr allwinner_h3_memmap[] = {
37 [AW_H3_DEV_SRAM_A1] = 0x00000000,
38 [AW_H3_DEV_SRAM_A2] = 0x00044000,
39 [AW_H3_DEV_SRAM_C] = 0x00010000,
40 [AW_H3_DEV_SYSCTRL] = 0x01c00000,
41 [AW_H3_DEV_MMC0] = 0x01c0f000,
42 [AW_H3_DEV_SID] = 0x01c14000,
43 [AW_H3_DEV_EHCI0] = 0x01c1a000,
44 [AW_H3_DEV_OHCI0] = 0x01c1a400,
45 [AW_H3_DEV_EHCI1] = 0x01c1b000,
46 [AW_H3_DEV_OHCI1] = 0x01c1b400,
47 [AW_H3_DEV_EHCI2] = 0x01c1c000,
48 [AW_H3_DEV_OHCI2] = 0x01c1c400,
49 [AW_H3_DEV_EHCI3] = 0x01c1d000,
50 [AW_H3_DEV_OHCI3] = 0x01c1d400,
51 [AW_H3_DEV_CCU] = 0x01c20000,
52 [AW_H3_DEV_PIT] = 0x01c20c00,
53 [AW_H3_DEV_UART0] = 0x01c28000,
54 [AW_H3_DEV_UART1] = 0x01c28400,
55 [AW_H3_DEV_UART2] = 0x01c28800,
56 [AW_H3_DEV_UART3] = 0x01c28c00,
57 [AW_H3_DEV_EMAC] = 0x01c30000,
58 [AW_H3_DEV_DRAMCOM] = 0x01c62000,
59 [AW_H3_DEV_DRAMCTL] = 0x01c63000,
60 [AW_H3_DEV_DRAMPHY] = 0x01c65000,
61 [AW_H3_DEV_GIC_DIST] = 0x01c81000,
62 [AW_H3_DEV_GIC_CPU] = 0x01c82000,
63 [AW_H3_DEV_GIC_HYP] = 0x01c84000,
64 [AW_H3_DEV_GIC_VCPU] = 0x01c86000,
65 [AW_H3_DEV_RTC] = 0x01f00000,
66 [AW_H3_DEV_CPUCFG] = 0x01f01c00,
67 [AW_H3_DEV_SDRAM] = 0x40000000
68 };
69
70 /* List of unimplemented devices */
71 struct AwH3Unimplemented {
72 const char *device_name;
73 hwaddr base;
74 hwaddr size;
75 } unimplemented[] = {
76 { "d-engine", 0x01000000, 4 * MiB },
77 { "d-inter", 0x01400000, 128 * KiB },
78 { "dma", 0x01c02000, 4 * KiB },
79 { "nfdc", 0x01c03000, 4 * KiB },
80 { "ts", 0x01c06000, 4 * KiB },
81 { "keymem", 0x01c0b000, 4 * KiB },
82 { "lcd0", 0x01c0c000, 4 * KiB },
83 { "lcd1", 0x01c0d000, 4 * KiB },
84 { "ve", 0x01c0e000, 4 * KiB },
85 { "mmc1", 0x01c10000, 4 * KiB },
86 { "mmc2", 0x01c11000, 4 * KiB },
87 { "crypto", 0x01c15000, 4 * KiB },
88 { "msgbox", 0x01c17000, 4 * KiB },
89 { "spinlock", 0x01c18000, 4 * KiB },
90 { "usb0-otg", 0x01c19000, 4 * KiB },
91 { "usb0-phy", 0x01c1a000, 4 * KiB },
92 { "usb1-phy", 0x01c1b000, 4 * KiB },
93 { "usb2-phy", 0x01c1c000, 4 * KiB },
94 { "usb3-phy", 0x01c1d000, 4 * KiB },
95 { "smc", 0x01c1e000, 4 * KiB },
96 { "pio", 0x01c20800, 1 * KiB },
97 { "owa", 0x01c21000, 1 * KiB },
98 { "pwm", 0x01c21400, 1 * KiB },
99 { "keyadc", 0x01c21800, 1 * KiB },
100 { "pcm0", 0x01c22000, 1 * KiB },
101 { "pcm1", 0x01c22400, 1 * KiB },
102 { "pcm2", 0x01c22800, 1 * KiB },
103 { "audio", 0x01c22c00, 2 * KiB },
104 { "smta", 0x01c23400, 1 * KiB },
105 { "ths", 0x01c25000, 1 * KiB },
106 { "uart0", 0x01c28000, 1 * KiB },
107 { "uart1", 0x01c28400, 1 * KiB },
108 { "uart2", 0x01c28800, 1 * KiB },
109 { "uart3", 0x01c28c00, 1 * KiB },
110 { "twi0", 0x01c2ac00, 1 * KiB },
111 { "twi1", 0x01c2b000, 1 * KiB },
112 { "twi2", 0x01c2b400, 1 * KiB },
113 { "scr", 0x01c2c400, 1 * KiB },
114 { "gpu", 0x01c40000, 64 * KiB },
115 { "hstmr", 0x01c60000, 4 * KiB },
116 { "spi0", 0x01c68000, 4 * KiB },
117 { "spi1", 0x01c69000, 4 * KiB },
118 { "csi", 0x01cb0000, 320 * KiB },
119 { "tve", 0x01e00000, 64 * KiB },
120 { "hdmi", 0x01ee0000, 128 * KiB },
121 { "r_timer", 0x01f00800, 1 * KiB },
122 { "r_intc", 0x01f00c00, 1 * KiB },
123 { "r_wdog", 0x01f01000, 1 * KiB },
124 { "r_prcm", 0x01f01400, 1 * KiB },
125 { "r_twd", 0x01f01800, 1 * KiB },
126 { "r_cir-rx", 0x01f02000, 1 * KiB },
127 { "r_twi", 0x01f02400, 1 * KiB },
128 { "r_uart", 0x01f02800, 1 * KiB },
129 { "r_pio", 0x01f02c00, 1 * KiB },
130 { "r_pwm", 0x01f03800, 1 * KiB },
131 { "core-dbg", 0x3f500000, 128 * KiB },
132 { "tsgen-ro", 0x3f506000, 4 * KiB },
133 { "tsgen-ctl", 0x3f507000, 4 * KiB },
134 { "ddr-mem", 0x40000000, 2 * GiB },
135 { "n-brom", 0xffff0000, 32 * KiB },
136 { "s-brom", 0xffff0000, 64 * KiB }
137 };
138
139 /* Per Processor Interrupts */
140 enum {
141 AW_H3_GIC_PPI_MAINT = 9,
142 AW_H3_GIC_PPI_HYPTIMER = 10,
143 AW_H3_GIC_PPI_VIRTTIMER = 11,
144 AW_H3_GIC_PPI_SECTIMER = 13,
145 AW_H3_GIC_PPI_PHYSTIMER = 14
146 };
147
148 /* Shared Processor Interrupts */
149 enum {
150 AW_H3_GIC_SPI_UART0 = 0,
151 AW_H3_GIC_SPI_UART1 = 1,
152 AW_H3_GIC_SPI_UART2 = 2,
153 AW_H3_GIC_SPI_UART3 = 3,
154 AW_H3_GIC_SPI_TIMER0 = 18,
155 AW_H3_GIC_SPI_TIMER1 = 19,
156 AW_H3_GIC_SPI_MMC0 = 60,
157 AW_H3_GIC_SPI_EHCI0 = 72,
158 AW_H3_GIC_SPI_OHCI0 = 73,
159 AW_H3_GIC_SPI_EHCI1 = 74,
160 AW_H3_GIC_SPI_OHCI1 = 75,
161 AW_H3_GIC_SPI_EHCI2 = 76,
162 AW_H3_GIC_SPI_OHCI2 = 77,
163 AW_H3_GIC_SPI_EHCI3 = 78,
164 AW_H3_GIC_SPI_OHCI3 = 79,
165 AW_H3_GIC_SPI_EMAC = 82
166 };
167
168 /* Allwinner H3 general constants */
169 enum {
170 AW_H3_GIC_NUM_SPI = 128
171 };
172
173 void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
174 {
175 const int64_t rom_size = 32 * KiB;
176 g_autofree uint8_t *buffer = g_new0(uint8_t, rom_size);
177
178 if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
179 error_setg(&error_fatal, "%s: failed to read BlockBackend data",
180 __func__);
181 return;
182 }
183
184 rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
185 rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
186 NULL, NULL, NULL, NULL, false);
187 }
188
189 static void allwinner_h3_init(Object *obj)
190 {
191 AwH3State *s = AW_H3(obj);
192
193 s->memmap = allwinner_h3_memmap;
194
195 for (int i = 0; i < AW_H3_NUM_CPUS; i++) {
196 object_initialize_child(obj, "cpu[*]", &s->cpus[i],
197 ARM_CPU_TYPE_NAME("cortex-a7"));
198 }
199
200 object_initialize_child(obj, "gic", &s->gic, TYPE_ARM_GIC);
201
202 object_initialize_child(obj, "timer", &s->timer, TYPE_AW_A10_PIT);
203 object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
204 "clk0-freq");
205 object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
206 "clk1-freq");
207
208 object_initialize_child(obj, "ccu", &s->ccu, TYPE_AW_H3_CCU);
209
210 object_initialize_child(obj, "sysctrl", &s->sysctrl, TYPE_AW_H3_SYSCTRL);
211
212 object_initialize_child(obj, "cpucfg", &s->cpucfg, TYPE_AW_CPUCFG);
213
214 object_initialize_child(obj, "sid", &s->sid, TYPE_AW_SID);
215 object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
216 "identifier");
217
218 object_initialize_child(obj, "mmc0", &s->mmc0, TYPE_AW_SDHOST_SUN5I);
219
220 object_initialize_child(obj, "emac", &s->emac, TYPE_AW_SUN8I_EMAC);
221
222 object_initialize_child(obj, "dramc", &s->dramc, TYPE_AW_H3_DRAMC);
223 object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
224 "ram-addr");
225 object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
226 "ram-size");
227
228 object_initialize_child(obj, "rtc", &s->rtc, TYPE_AW_RTC_SUN6I);
229 }
230
231 static void allwinner_h3_realize(DeviceState *dev, Error **errp)
232 {
233 AwH3State *s = AW_H3(dev);
234 unsigned i;
235
236 /* CPUs */
237 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
238
239 /* Provide Power State Coordination Interface */
240 qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
241 QEMU_PSCI_CONDUIT_HVC);
242
243 /* Disable secondary CPUs */
244 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
245 i > 0);
246
247 /* All exception levels required */
248 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
249 qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
250
251 /* Mark realized */
252 qdev_realize(DEVICE(&s->cpus[i]), NULL, &error_fatal);
253 }
254
255 /* Generic Interrupt Controller */
256 qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
257 GIC_INTERNAL);
258 qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
259 qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
260 qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
261 qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
262 sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
263
264 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
265 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
266 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
267 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
268
269 /*
270 * Wire the outputs from each CPU's generic timer and the GICv3
271 * maintenance interrupt signal to the appropriate GIC PPI inputs,
272 * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs.
273 */
274 for (i = 0; i < AW_H3_NUM_CPUS; i++) {
275 DeviceState *cpudev = DEVICE(&s->cpus[i]);
276 int ppibase = AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
277 int irq;
278 /*
279 * Mapping from the output timer irq lines from the CPU to the
280 * GIC PPI inputs used for this board.
281 */
282 const int timer_irq[] = {
283 [GTIMER_PHYS] = AW_H3_GIC_PPI_PHYSTIMER,
284 [GTIMER_VIRT] = AW_H3_GIC_PPI_VIRTTIMER,
285 [GTIMER_HYP] = AW_H3_GIC_PPI_HYPTIMER,
286 [GTIMER_SEC] = AW_H3_GIC_PPI_SECTIMER,
287 };
288
289 /* Connect CPU timer outputs to GIC PPI inputs */
290 for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
291 qdev_connect_gpio_out(cpudev, irq,
292 qdev_get_gpio_in(DEVICE(&s->gic),
293 ppibase + timer_irq[irq]));
294 }
295
296 /* Connect GIC outputs to CPU interrupt inputs */
297 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
298 qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
299 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
300 qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
301 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPUS),
302 qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
303 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPUS),
304 qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
305
306 /* GIC maintenance signal */
307 sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPUS),
308 qdev_get_gpio_in(DEVICE(&s->gic),
309 ppibase + AW_H3_GIC_PPI_MAINT));
310 }
311
312 /* Timer */
313 sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
314 sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
315 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
316 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
317 sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
318 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER1));
319
320 /* SRAM */
321 memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
322 64 * KiB, &error_abort);
323 memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
324 32 * KiB, &error_abort);
325 memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
326 44 * KiB, &error_abort);
327 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
328 &s->sram_a1);
329 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
330 &s->sram_a2);
331 memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
332 &s->sram_c);
333
334 /* Clock Control Unit */
335 sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
336 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
337
338 /* System Control */
339 sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
340 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
341
342 /* CPU Configuration */
343 sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
344 sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
345
346 /* Security Identifier */
347 sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
348 sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
349
350 /* SD/MMC */
351 object_property_set_link(OBJECT(&s->mmc0), "dma-memory",
352 OBJECT(get_system_memory()), &error_fatal);
353 sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
354 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
355 sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
356 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
357
358 object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
359 "sd-bus");
360
361 /* EMAC */
362 /* FIXME use qdev NIC properties instead of nd_table[] */
363 if (nd_table[0].used) {
364 qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
365 qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
366 }
367 object_property_set_link(OBJECT(&s->emac), "dma-memory",
368 OBJECT(get_system_memory()), &error_fatal);
369 sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
370 sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
371 sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
372 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
373
374 /* Universal Serial Bus */
375 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
376 qdev_get_gpio_in(DEVICE(&s->gic),
377 AW_H3_GIC_SPI_EHCI0));
378 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
379 qdev_get_gpio_in(DEVICE(&s->gic),
380 AW_H3_GIC_SPI_EHCI1));
381 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
382 qdev_get_gpio_in(DEVICE(&s->gic),
383 AW_H3_GIC_SPI_EHCI2));
384 sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
385 qdev_get_gpio_in(DEVICE(&s->gic),
386 AW_H3_GIC_SPI_EHCI3));
387
388 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
389 qdev_get_gpio_in(DEVICE(&s->gic),
390 AW_H3_GIC_SPI_OHCI0));
391 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
392 qdev_get_gpio_in(DEVICE(&s->gic),
393 AW_H3_GIC_SPI_OHCI1));
394 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
395 qdev_get_gpio_in(DEVICE(&s->gic),
396 AW_H3_GIC_SPI_OHCI2));
397 sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
398 qdev_get_gpio_in(DEVICE(&s->gic),
399 AW_H3_GIC_SPI_OHCI3));
400
401 /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
402 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
403 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
404 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
405 /* UART1 */
406 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
407 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
408 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
409 /* UART2 */
410 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
411 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
412 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
413 /* UART3 */
414 serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
415 qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
416 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
417
418 /* DRAMC */
419 sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
420 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
421 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
422 sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
423
424 /* RTC */
425 sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
427
428 /* Unimplemented devices */
429 for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {
430 create_unimplemented_device(unimplemented[i].device_name,
431 unimplemented[i].base,
432 unimplemented[i].size);
433 }
434 }
435
436 static void allwinner_h3_class_init(ObjectClass *oc, void *data)
437 {
438 DeviceClass *dc = DEVICE_CLASS(oc);
439
440 dc->realize = allwinner_h3_realize;
441 /* Reason: uses serial_hd() in realize function */
442 dc->user_creatable = false;
443 }
444
445 static const TypeInfo allwinner_h3_type_info = {
446 .name = TYPE_AW_H3,
447 .parent = TYPE_DEVICE,
448 .instance_size = sizeof(AwH3State),
449 .instance_init = allwinner_h3_init,
450 .class_init = allwinner_h3_class_init,
451 };
452
453 static void allwinner_h3_register_types(void)
454 {
455 type_register_static(&allwinner_h3_type_info);
456 }
457
458 type_init(allwinner_h3_register_types)
AR7 emulation for QEMU