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net: checksum: Skip fragmented IP packets
[qemu/ar7.git] / hw / arm / npcm7xx.c
blob72040d40799d1b7084a3074b3a691bd905ea767a
1 /*
2 * Nuvoton NPCM7xx SoC family.
3 *
4 * Copyright 2020 Google LLC
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 */
16
17 #include "qemu/osdep.h"
18
19 #include "exec/address-spaces.h"
20 #include "hw/arm/boot.h"
21 #include "hw/arm/npcm7xx.h"
22 #include "hw/char/serial.h"
23 #include "hw/loader.h"
24 #include "hw/misc/unimp.h"
25 #include "hw/qdev-clock.h"
26 #include "hw/qdev-properties.h"
27 #include "qapi/error.h"
28 #include "qemu/units.h"
29 #include "sysemu/sysemu.h"
30
31 /*
32 * This covers the whole MMIO space. We'll use this to catch any MMIO accesses
33 * that aren't handled by any device.
34 */
35 #define NPCM7XX_MMIO_BA (0x80000000)
36 #define NPCM7XX_MMIO_SZ (0x7ffd0000)
37
38 /* OTP key storage and fuse strap array */
39 #define NPCM7XX_OTP1_BA (0xf0189000)
40 #define NPCM7XX_OTP2_BA (0xf018a000)
41
42 /* Core system modules. */
43 #define NPCM7XX_L2C_BA (0xf03fc000)
44 #define NPCM7XX_CPUP_BA (0xf03fe000)
45 #define NPCM7XX_GCR_BA (0xf0800000)
46 #define NPCM7XX_CLK_BA (0xf0801000)
47 #define NPCM7XX_MC_BA (0xf0824000)
48 #define NPCM7XX_RNG_BA (0xf000b000)
49
50 /* USB Host modules */
51 #define NPCM7XX_EHCI_BA (0xf0806000)
52 #define NPCM7XX_OHCI_BA (0xf0807000)
53
54 /* ADC Module */
55 #define NPCM7XX_ADC_BA (0xf000c000)
56
57 /* Internal AHB SRAM */
58 #define NPCM7XX_RAM3_BA (0xc0008000)
59 #define NPCM7XX_RAM3_SZ (4 * KiB)
60
61 /* Memory blocks at the end of the address space */
62 #define NPCM7XX_RAM2_BA (0xfffd0000)
63 #define NPCM7XX_RAM2_SZ (128 * KiB)
64 #define NPCM7XX_ROM_BA (0xffff0000)
65 #define NPCM7XX_ROM_SZ (64 * KiB)
66
67
68 /* Clock configuration values to be fixed up when bypassing bootloader */
69
70 /* Run PLL1 at 1600 MHz */
71 #define NPCM7XX_PLLCON1_FIXUP_VAL (0x00402101)
72 /* Run the CPU from PLL1 and UART from PLL2 */
73 #define NPCM7XX_CLKSEL_FIXUP_VAL (0x004aaba9)
74
75 /*
76 * Interrupt lines going into the GIC. This does not include internal Cortex-A9
77 * interrupts.
78 */
79 enum NPCM7xxInterrupt {
80 NPCM7XX_ADC_IRQ = 0,
81 NPCM7XX_UART0_IRQ = 2,
82 NPCM7XX_UART1_IRQ,
83 NPCM7XX_UART2_IRQ,
84 NPCM7XX_UART3_IRQ,
85 NPCM7XX_TIMER0_IRQ = 32, /* Timer Module 0 */
86 NPCM7XX_TIMER1_IRQ,
87 NPCM7XX_TIMER2_IRQ,
88 NPCM7XX_TIMER3_IRQ,
89 NPCM7XX_TIMER4_IRQ,
90 NPCM7XX_TIMER5_IRQ, /* Timer Module 1 */
91 NPCM7XX_TIMER6_IRQ,
92 NPCM7XX_TIMER7_IRQ,
93 NPCM7XX_TIMER8_IRQ,
94 NPCM7XX_TIMER9_IRQ,
95 NPCM7XX_TIMER10_IRQ, /* Timer Module 2 */
96 NPCM7XX_TIMER11_IRQ,
97 NPCM7XX_TIMER12_IRQ,
98 NPCM7XX_TIMER13_IRQ,
99 NPCM7XX_TIMER14_IRQ,
100 NPCM7XX_WDG0_IRQ = 47, /* Timer Module 0 Watchdog */
101 NPCM7XX_WDG1_IRQ, /* Timer Module 1 Watchdog */
102 NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
103 NPCM7XX_EHCI_IRQ = 61,
104 NPCM7XX_OHCI_IRQ = 62,
105 NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
106 NPCM7XX_PWM1_IRQ, /* PWM module 1 */
107 NPCM7XX_GPIO0_IRQ = 116,
108 NPCM7XX_GPIO1_IRQ,
109 NPCM7XX_GPIO2_IRQ,
110 NPCM7XX_GPIO3_IRQ,
111 NPCM7XX_GPIO4_IRQ,
112 NPCM7XX_GPIO5_IRQ,
113 NPCM7XX_GPIO6_IRQ,
114 NPCM7XX_GPIO7_IRQ,
115 };
116
117 /* Total number of GIC interrupts, including internal Cortex-A9 interrupts. */
118 #define NPCM7XX_NUM_IRQ (160)
119
120 /* Register base address for each Timer Module */
121 static const hwaddr npcm7xx_tim_addr[] = {
122 0xf0008000,
123 0xf0009000,
124 0xf000a000,
125 };
126
127 /* Register base address for each 16550 UART */
128 static const hwaddr npcm7xx_uart_addr[] = {
129 0xf0001000,
130 0xf0002000,
131 0xf0003000,
132 0xf0004000,
133 };
134
135 /* Direct memory-mapped access to SPI0 CS0-1. */
136 static const hwaddr npcm7xx_fiu0_flash_addr[] = {
137 0x80000000, /* CS0 */
138 0x88000000, /* CS1 */
139 };
140
141 /* Direct memory-mapped access to SPI3 CS0-3. */
142 static const hwaddr npcm7xx_fiu3_flash_addr[] = {
143 0xa0000000, /* CS0 */
144 0xa8000000, /* CS1 */
145 0xb0000000, /* CS2 */
146 0xb8000000, /* CS3 */
147 };
148
149 /* Register base address for each PWM Module */
150 static const hwaddr npcm7xx_pwm_addr[] = {
151 0xf0103000,
152 0xf0104000,
153 };
154
155 static const struct {
156 hwaddr regs_addr;
157 uint32_t unconnected_pins;
158 uint32_t reset_pu;
159 uint32_t reset_pd;
160 uint32_t reset_osrc;
161 uint32_t reset_odsc;
162 } npcm7xx_gpio[] = {
163 {
164 .regs_addr = 0xf0010000,
165 .reset_pu = 0xff03ffff,
166 .reset_pd = 0x00fc0000,
167 }, {
168 .regs_addr = 0xf0011000,
169 .unconnected_pins = 0x0000001e,
170 .reset_pu = 0xfefffe07,
171 .reset_pd = 0x010001e0,
172 }, {
173 .regs_addr = 0xf0012000,
174 .reset_pu = 0x780fffff,
175 .reset_pd = 0x07f00000,
176 .reset_odsc = 0x00700000,
177 }, {
178 .regs_addr = 0xf0013000,
179 .reset_pu = 0x00fc0000,
180 .reset_pd = 0xff000000,
181 }, {
182 .regs_addr = 0xf0014000,
183 .reset_pu = 0xffffffff,
184 }, {
185 .regs_addr = 0xf0015000,
186 .reset_pu = 0xbf83f801,
187 .reset_pd = 0x007c0000,
188 .reset_osrc = 0x000000f1,
189 .reset_odsc = 0x3f9f80f1,
190 }, {
191 .regs_addr = 0xf0016000,
192 .reset_pu = 0xfc00f801,
193 .reset_pd = 0x000007fe,
194 .reset_odsc = 0x00000800,
195 }, {
196 .regs_addr = 0xf0017000,
197 .unconnected_pins = 0xffffff00,
198 .reset_pu = 0x0000007f,
199 .reset_osrc = 0x0000007f,
200 .reset_odsc = 0x0000007f,
201 },
202 };
203
204 static const struct {
205 const char *name;
206 hwaddr regs_addr;
207 int cs_count;
208 const hwaddr *flash_addr;
209 } npcm7xx_fiu[] = {
210 {
211 .name = "fiu0",
212 .regs_addr = 0xfb000000,
213 .cs_count = ARRAY_SIZE(npcm7xx_fiu0_flash_addr),
214 .flash_addr = npcm7xx_fiu0_flash_addr,
215 }, {
216 .name = "fiu3",
217 .regs_addr = 0xc0000000,
218 .cs_count = ARRAY_SIZE(npcm7xx_fiu3_flash_addr),
219 .flash_addr = npcm7xx_fiu3_flash_addr,
220 },
221 };
222
223 static void npcm7xx_write_board_setup(ARMCPU *cpu,
224 const struct arm_boot_info *info)
225 {
226 uint32_t board_setup[] = {
227 0xe59f0010, /* ldr r0, clk_base_addr */
228 0xe59f1010, /* ldr r1, pllcon1_value */
229 0xe5801010, /* str r1, [r0, #16] */
230 0xe59f100c, /* ldr r1, clksel_value */
231 0xe5801004, /* str r1, [r0, #4] */
232 0xe12fff1e, /* bx lr */
233 NPCM7XX_CLK_BA,
234 NPCM7XX_PLLCON1_FIXUP_VAL,
235 NPCM7XX_CLKSEL_FIXUP_VAL,
236 };
237 int i;
238
239 for (i = 0; i < ARRAY_SIZE(board_setup); i++) {
240 board_setup[i] = tswap32(board_setup[i]);
241 }
242 rom_add_blob_fixed("board-setup", board_setup, sizeof(board_setup),
243 info->board_setup_addr);
244 }
245
246 static void npcm7xx_write_secondary_boot(ARMCPU *cpu,
247 const struct arm_boot_info *info)
248 {
249 /*
250 * The default smpboot stub halts the secondary CPU with a 'wfi'
251 * instruction, but the arch/arm/mach-npcm/platsmp.c in the Linux kernel
252 * does not send an IPI to wake it up, so the second CPU fails to boot. So
253 * we need to provide our own smpboot stub that can not use 'wfi', it has
254 * to spin the secondary CPU until the first CPU writes to the SCRPAD reg.
255 */
256 uint32_t smpboot[] = {
257 0xe59f2018, /* ldr r2, bootreg_addr */
258 0xe3a00000, /* mov r0, #0 */
259 0xe5820000, /* str r0, [r2] */
260 0xe320f002, /* wfe */
261 0xe5921000, /* ldr r1, [r2] */
262 0xe1110001, /* tst r1, r1 */
263 0x0afffffb, /* beq <wfe> */
264 0xe12fff11, /* bx r1 */
265 NPCM7XX_SMP_BOOTREG_ADDR,
266 };
267 int i;
268
269 for (i = 0; i < ARRAY_SIZE(smpboot); i++) {
270 smpboot[i] = tswap32(smpboot[i]);
271 }
272
273 rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot),
274 NPCM7XX_SMP_LOADER_START);
275 }
276
277 static struct arm_boot_info npcm7xx_binfo = {
278 .loader_start = NPCM7XX_LOADER_START,
279 .smp_loader_start = NPCM7XX_SMP_LOADER_START,
280 .smp_bootreg_addr = NPCM7XX_SMP_BOOTREG_ADDR,
281 .gic_cpu_if_addr = NPCM7XX_GIC_CPU_IF_ADDR,
282 .write_secondary_boot = npcm7xx_write_secondary_boot,
283 .board_id = -1,
284 .board_setup_addr = NPCM7XX_BOARD_SETUP_ADDR,
285 .write_board_setup = npcm7xx_write_board_setup,
286 };
287
288 void npcm7xx_load_kernel(MachineState *machine, NPCM7xxState *soc)
289 {
290 NPCM7xxClass *sc = NPCM7XX_GET_CLASS(soc);
291
292 npcm7xx_binfo.ram_size = machine->ram_size;
293 npcm7xx_binfo.nb_cpus = sc->num_cpus;
294
295 arm_load_kernel(&soc->cpu[0], machine, &npcm7xx_binfo);
296 }
297
298 static void npcm7xx_init_fuses(NPCM7xxState *s)
299 {
300 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
301 uint32_t value;
302
303 /*
304 * The initial mask of disabled modules indicates the chip derivative (e.g.
305 * NPCM750 or NPCM730).
306 */
307 value = tswap32(nc->disabled_modules);
308 npcm7xx_otp_array_write(&s->fuse_array, &value, NPCM7XX_FUSE_DERIVATIVE,
309 sizeof(value));
310 }
311
312 static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
313 {
314 /* Both ADC and the fuse array must have realized. */
315 QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
316 npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
317 NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
318 }
319
320 static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
321 {
322 return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
323 }
324
325 static void npcm7xx_init(Object *obj)
326 {
327 NPCM7xxState *s = NPCM7XX(obj);
328 int i;
329
330 for (i = 0; i < NPCM7XX_MAX_NUM_CPUS; i++) {
331 object_initialize_child(obj, "cpu[*]", &s->cpu[i],
332 ARM_CPU_TYPE_NAME("cortex-a9"));
333 }
334
335 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_PRIV);
336 object_initialize_child(obj, "gcr", &s->gcr, TYPE_NPCM7XX_GCR);
337 object_property_add_alias(obj, "power-on-straps", OBJECT(&s->gcr),
338 "power-on-straps");
339 object_initialize_child(obj, "clk", &s->clk, TYPE_NPCM7XX_CLK);
340 object_initialize_child(obj, "otp1", &s->key_storage,
341 TYPE_NPCM7XX_KEY_STORAGE);
342 object_initialize_child(obj, "otp2", &s->fuse_array,
343 TYPE_NPCM7XX_FUSE_ARRAY);
344 object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
345 object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
346 object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
347
348 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
349 object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
350 }
351
352 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
353 object_initialize_child(obj, "gpio[*]", &s->gpio[i], TYPE_NPCM7XX_GPIO);
354 }
355
356 object_initialize_child(obj, "ehci", &s->ehci, TYPE_NPCM7XX_EHCI);
357 object_initialize_child(obj, "ohci", &s->ohci, TYPE_SYSBUS_OHCI);
358
359 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
360 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
361 object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
362 TYPE_NPCM7XX_FIU);
363 }
364
365 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
366 object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
367 }
368 }
369
370 static void npcm7xx_realize(DeviceState *dev, Error **errp)
371 {
372 NPCM7xxState *s = NPCM7XX(dev);
373 NPCM7xxClass *nc = NPCM7XX_GET_CLASS(s);
374 int i;
375
376 if (memory_region_size(s->dram) > NPCM7XX_DRAM_SZ) {
377 error_setg(errp, "%s: NPCM7xx cannot address more than %" PRIu64
378 " MiB of DRAM", __func__, NPCM7XX_DRAM_SZ / MiB);
379 return;
380 }
381
382 /* CPUs */
383 for (i = 0; i < nc->num_cpus; i++) {
384 object_property_set_int(OBJECT(&s->cpu[i]), "mp-affinity",
385 arm_cpu_mp_affinity(i, NPCM7XX_MAX_NUM_CPUS),
386 &error_abort);
387 object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar",
388 NPCM7XX_GIC_CPU_IF_ADDR, &error_abort);
389 object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true,
390 &error_abort);
391
392 /* Disable security extensions. */
393 object_property_set_bool(OBJECT(&s->cpu[i]), "has_el3", false,
394 &error_abort);
395
396 if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
397 return;
398 }
399 }
400
401 /* A9MPCORE peripherals. Can only fail if we pass bad parameters here. */
402 object_property_set_int(OBJECT(&s->a9mpcore), "num-cpu", nc->num_cpus,
403 &error_abort);
404 object_property_set_int(OBJECT(&s->a9mpcore), "num-irq", NPCM7XX_NUM_IRQ,
405 &error_abort);
406 sysbus_realize(SYS_BUS_DEVICE(&s->a9mpcore), &error_abort);
407 sysbus_mmio_map(SYS_BUS_DEVICE(&s->a9mpcore), 0, NPCM7XX_CPUP_BA);
408
409 for (i = 0; i < nc->num_cpus; i++) {
410 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i,
411 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_IRQ));
412 sysbus_connect_irq(SYS_BUS_DEVICE(&s->a9mpcore), i + nc->num_cpus,
413 qdev_get_gpio_in(DEVICE(&s->cpu[i]), ARM_CPU_FIQ));
414 }
415
416 /* L2 cache controller */
417 sysbus_create_simple("l2x0", NPCM7XX_L2C_BA, NULL);
418
419 /* System Global Control Registers (GCR). Can fail due to user input. */
420 object_property_set_int(OBJECT(&s->gcr), "disabled-modules",
421 nc->disabled_modules, &error_abort);
422 object_property_add_const_link(OBJECT(&s->gcr), "dram-mr", OBJECT(s->dram));
423 if (!sysbus_realize(SYS_BUS_DEVICE(&s->gcr), errp)) {
424 return;
425 }
426 sysbus_mmio_map(SYS_BUS_DEVICE(&s->gcr), 0, NPCM7XX_GCR_BA);
427
428 /* Clock Control Registers (CLK). Cannot fail. */
429 sysbus_realize(SYS_BUS_DEVICE(&s->clk), &error_abort);
430 sysbus_mmio_map(SYS_BUS_DEVICE(&s->clk), 0, NPCM7XX_CLK_BA);
431
432 /* OTP key storage and fuse strap array. Cannot fail. */
433 sysbus_realize(SYS_BUS_DEVICE(&s->key_storage), &error_abort);
434 sysbus_mmio_map(SYS_BUS_DEVICE(&s->key_storage), 0, NPCM7XX_OTP1_BA);
435 sysbus_realize(SYS_BUS_DEVICE(&s->fuse_array), &error_abort);
436 sysbus_mmio_map(SYS_BUS_DEVICE(&s->fuse_array), 0, NPCM7XX_OTP2_BA);
437 npcm7xx_init_fuses(s);
438
439 /* Fake Memory Controller (MC). Cannot fail. */
440 sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
441 sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
442
443 /* ADC Modules. Cannot fail. */
444 qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
445 DEVICE(&s->clk), "adc-clock"));
446 sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
447 sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
448 sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
449 npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
450 npcm7xx_write_adc_calibration(s);
451
452 /* Timer Modules (TIM). Cannot fail. */
453 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
454 for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
455 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->tim[i]);
456 int first_irq;
457 int j;
458
459 /* Connect the timer clock. */
460 qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
461 DEVICE(&s->clk), "timer-clock"));
462
463 sysbus_realize(sbd, &error_abort);
464 sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
465
466 first_irq = NPCM7XX_TIMER0_IRQ + i * NPCM7XX_TIMERS_PER_CTRL;
467 for (j = 0; j < NPCM7XX_TIMERS_PER_CTRL; j++) {
468 qemu_irq irq = npcm7xx_irq(s, first_irq + j);
469 sysbus_connect_irq(sbd, j, irq);
470 }
471
472 /* IRQ for watchdogs */
473 sysbus_connect_irq(sbd, NPCM7XX_TIMERS_PER_CTRL,
474 npcm7xx_irq(s, NPCM7XX_WDG0_IRQ + i));
475 /* GPIO that connects clk module with watchdog */
476 qdev_connect_gpio_out_named(DEVICE(&s->tim[i]),
477 NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 0,
478 qdev_get_gpio_in_named(DEVICE(&s->clk),
479 NPCM7XX_WATCHDOG_RESET_GPIO_IN, i));
480 }
481
482 /* UART0..3 (16550 compatible) */
483 for (i = 0; i < ARRAY_SIZE(npcm7xx_uart_addr); i++) {
484 serial_mm_init(get_system_memory(), npcm7xx_uart_addr[i], 2,
485 npcm7xx_irq(s, NPCM7XX_UART0_IRQ + i), 115200,
486 serial_hd(i), DEVICE_LITTLE_ENDIAN);
487 }
488
489 /* Random Number Generator. Cannot fail. */
490 sysbus_realize(SYS_BUS_DEVICE(&s->rng), &error_abort);
491 sysbus_mmio_map(SYS_BUS_DEVICE(&s->rng), 0, NPCM7XX_RNG_BA);
492
493 /* GPIO modules. Cannot fail. */
494 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_gpio) != ARRAY_SIZE(s->gpio));
495 for (i = 0; i < ARRAY_SIZE(s->gpio); i++) {
496 Object *obj = OBJECT(&s->gpio[i]);
497
498 object_property_set_uint(obj, "reset-pullup",
499 npcm7xx_gpio[i].reset_pu, &error_abort);
500 object_property_set_uint(obj, "reset-pulldown",
501 npcm7xx_gpio[i].reset_pd, &error_abort);
502 object_property_set_uint(obj, "reset-osrc",
503 npcm7xx_gpio[i].reset_osrc, &error_abort);
504 object_property_set_uint(obj, "reset-odsc",
505 npcm7xx_gpio[i].reset_odsc, &error_abort);
506 sysbus_realize(SYS_BUS_DEVICE(obj), &error_abort);
507 sysbus_mmio_map(SYS_BUS_DEVICE(obj), 0, npcm7xx_gpio[i].regs_addr);
508 sysbus_connect_irq(SYS_BUS_DEVICE(obj), 0,
509 npcm7xx_irq(s, NPCM7XX_GPIO0_IRQ + i));
510 }
511
512 /* USB Host */
513 object_property_set_bool(OBJECT(&s->ehci), "companion-enable", true,
514 &error_abort);
515 sysbus_realize(SYS_BUS_DEVICE(&s->ehci), &error_abort);
516 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci), 0, NPCM7XX_EHCI_BA);
517 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci), 0,
518 npcm7xx_irq(s, NPCM7XX_EHCI_IRQ));
519
520 object_property_set_str(OBJECT(&s->ohci), "masterbus", "usb-bus.0",
521 &error_abort);
522 object_property_set_uint(OBJECT(&s->ohci), "num-ports", 1, &error_abort);
523 sysbus_realize(SYS_BUS_DEVICE(&s->ohci), &error_abort);
524 sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci), 0, NPCM7XX_OHCI_BA);
525 sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
526 npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
527
528 /* PWM Modules. Cannot fail. */
529 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
530 for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
531 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
532
533 qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
534 DEVICE(&s->clk), "apb3-clock"));
535 sysbus_realize(sbd, &error_abort);
536 sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
537 sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
538 }
539
540 /*
541 * Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
542 * specified, but this is a programming error.
543 */
544 QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_fiu) != ARRAY_SIZE(s->fiu));
545 for (i = 0; i < ARRAY_SIZE(s->fiu); i++) {
546 SysBusDevice *sbd = SYS_BUS_DEVICE(&s->fiu[i]);
547 int j;
548
549 object_property_set_int(OBJECT(sbd), "cs-count",
550 npcm7xx_fiu[i].cs_count, &error_abort);
551 sysbus_realize(sbd, &error_abort);
552
553 sysbus_mmio_map(sbd, 0, npcm7xx_fiu[i].regs_addr);
554 for (j = 0; j < npcm7xx_fiu[i].cs_count; j++) {
555 sysbus_mmio_map(sbd, j + 1, npcm7xx_fiu[i].flash_addr[j]);
556 }
557 }
558
559 /* RAM2 (SRAM) */
560 memory_region_init_ram(&s->sram, OBJECT(dev), "ram2",
561 NPCM7XX_RAM2_SZ, &error_abort);
562 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM2_BA, &s->sram);
563
564 /* RAM3 (SRAM) */
565 memory_region_init_ram(&s->ram3, OBJECT(dev), "ram3",
566 NPCM7XX_RAM3_SZ, &error_abort);
567 memory_region_add_subregion(get_system_memory(), NPCM7XX_RAM3_BA, &s->ram3);
568
569 /* Internal ROM */
570 memory_region_init_rom(&s->irom, OBJECT(dev), "irom", NPCM7XX_ROM_SZ,
571 &error_abort);
572 memory_region_add_subregion(get_system_memory(), NPCM7XX_ROM_BA, &s->irom);
573
574 create_unimplemented_device("npcm7xx.shm", 0xc0001000, 4 * KiB);
575 create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
576 create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
577 create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
578 create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
579 create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
580 create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
581 create_unimplemented_device("npcm7xx.gpio[2]", 0xf0012000, 4 * KiB);
582 create_unimplemented_device("npcm7xx.gpio[3]", 0xf0013000, 4 * KiB);
583 create_unimplemented_device("npcm7xx.gpio[4]", 0xf0014000, 4 * KiB);
584 create_unimplemented_device("npcm7xx.gpio[5]", 0xf0015000, 4 * KiB);
585 create_unimplemented_device("npcm7xx.gpio[6]", 0xf0016000, 4 * KiB);
586 create_unimplemented_device("npcm7xx.gpio[7]", 0xf0017000, 4 * KiB);
587 create_unimplemented_device("npcm7xx.smbus[0]", 0xf0080000, 4 * KiB);
588 create_unimplemented_device("npcm7xx.smbus[1]", 0xf0081000, 4 * KiB);
589 create_unimplemented_device("npcm7xx.smbus[2]", 0xf0082000, 4 * KiB);
590 create_unimplemented_device("npcm7xx.smbus[3]", 0xf0083000, 4 * KiB);
591 create_unimplemented_device("npcm7xx.smbus[4]", 0xf0084000, 4 * KiB);
592 create_unimplemented_device("npcm7xx.smbus[5]", 0xf0085000, 4 * KiB);
593 create_unimplemented_device("npcm7xx.smbus[6]", 0xf0086000, 4 * KiB);
594 create_unimplemented_device("npcm7xx.smbus[7]", 0xf0087000, 4 * KiB);
595 create_unimplemented_device("npcm7xx.smbus[8]", 0xf0088000, 4 * KiB);
596 create_unimplemented_device("npcm7xx.smbus[9]", 0xf0089000, 4 * KiB);
597 create_unimplemented_device("npcm7xx.smbus[10]", 0xf008a000, 4 * KiB);
598 create_unimplemented_device("npcm7xx.smbus[11]", 0xf008b000, 4 * KiB);
599 create_unimplemented_device("npcm7xx.smbus[12]", 0xf008c000, 4 * KiB);
600 create_unimplemented_device("npcm7xx.smbus[13]", 0xf008d000, 4 * KiB);
601 create_unimplemented_device("npcm7xx.smbus[14]", 0xf008e000, 4 * KiB);
602 create_unimplemented_device("npcm7xx.smbus[15]", 0xf008f000, 4 * KiB);
603 create_unimplemented_device("npcm7xx.espi", 0xf009f000, 4 * KiB);
604 create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
605 create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
606 create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
607 create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
608 create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
609 create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
610 create_unimplemented_device("npcm7xx.mft[3]", 0xf0183000, 4 * KiB);
611 create_unimplemented_device("npcm7xx.mft[4]", 0xf0184000, 4 * KiB);
612 create_unimplemented_device("npcm7xx.mft[5]", 0xf0185000, 4 * KiB);
613 create_unimplemented_device("npcm7xx.mft[6]", 0xf0186000, 4 * KiB);
614 create_unimplemented_device("npcm7xx.mft[7]", 0xf0187000, 4 * KiB);
615 create_unimplemented_device("npcm7xx.pspi1", 0xf0200000, 4 * KiB);
616 create_unimplemented_device("npcm7xx.pspi2", 0xf0201000, 4 * KiB);
617 create_unimplemented_device("npcm7xx.ahbpci", 0xf0400000, 1 * MiB);
618 create_unimplemented_device("npcm7xx.mcphy", 0xf05f0000, 64 * KiB);
619 create_unimplemented_device("npcm7xx.gmac1", 0xf0802000, 8 * KiB);
620 create_unimplemented_device("npcm7xx.gmac2", 0xf0804000, 8 * KiB);
621 create_unimplemented_device("npcm7xx.vcd", 0xf0810000, 64 * KiB);
622 create_unimplemented_device("npcm7xx.ece", 0xf0820000, 8 * KiB);
623 create_unimplemented_device("npcm7xx.vdma", 0xf0822000, 8 * KiB);
624 create_unimplemented_device("npcm7xx.emc1", 0xf0825000, 4 * KiB);
625 create_unimplemented_device("npcm7xx.emc2", 0xf0826000, 4 * KiB);
626 create_unimplemented_device("npcm7xx.usbd[0]", 0xf0830000, 4 * KiB);
627 create_unimplemented_device("npcm7xx.usbd[1]", 0xf0831000, 4 * KiB);
628 create_unimplemented_device("npcm7xx.usbd[2]", 0xf0832000, 4 * KiB);
629 create_unimplemented_device("npcm7xx.usbd[3]", 0xf0833000, 4 * KiB);
630 create_unimplemented_device("npcm7xx.usbd[4]", 0xf0834000, 4 * KiB);
631 create_unimplemented_device("npcm7xx.usbd[5]", 0xf0835000, 4 * KiB);
632 create_unimplemented_device("npcm7xx.usbd[6]", 0xf0836000, 4 * KiB);
633 create_unimplemented_device("npcm7xx.usbd[7]", 0xf0837000, 4 * KiB);
634 create_unimplemented_device("npcm7xx.usbd[8]", 0xf0838000, 4 * KiB);
635 create_unimplemented_device("npcm7xx.usbd[9]", 0xf0839000, 4 * KiB);
636 create_unimplemented_device("npcm7xx.sd", 0xf0840000, 8 * KiB);
637 create_unimplemented_device("npcm7xx.mmc", 0xf0842000, 8 * KiB);
638 create_unimplemented_device("npcm7xx.pcimbx", 0xf0848000, 512 * KiB);
639 create_unimplemented_device("npcm7xx.aes", 0xf0858000, 4 * KiB);
640 create_unimplemented_device("npcm7xx.des", 0xf0859000, 4 * KiB);
641 create_unimplemented_device("npcm7xx.sha", 0xf085a000, 4 * KiB);
642 create_unimplemented_device("npcm7xx.secacc", 0xf085b000, 4 * KiB);
643 create_unimplemented_device("npcm7xx.spixcs0", 0xf8000000, 16 * MiB);
644 create_unimplemented_device("npcm7xx.spixcs1", 0xf9000000, 16 * MiB);
645 create_unimplemented_device("npcm7xx.spix", 0xfb001000, 4 * KiB);
646 }
647
648 static Property npcm7xx_properties[] = {
649 DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION,
650 MemoryRegion *),
651 DEFINE_PROP_END_OF_LIST(),
652 };
653
654 static void npcm7xx_class_init(ObjectClass *oc, void *data)
655 {
656 DeviceClass *dc = DEVICE_CLASS(oc);
657
658 dc->realize = npcm7xx_realize;
659 dc->user_creatable = false;
660 device_class_set_props(dc, npcm7xx_properties);
661 }
662
663 static void npcm730_class_init(ObjectClass *oc, void *data)
664 {
665 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
666
667 /* NPCM730 is optimized for data center use, so no graphics, etc. */
668 nc->disabled_modules = 0x00300395;
669 nc->num_cpus = 2;
670 }
671
672 static void npcm750_class_init(ObjectClass *oc, void *data)
673 {
674 NPCM7xxClass *nc = NPCM7XX_CLASS(oc);
675
676 /* NPCM750 has 2 cores and a full set of peripherals */
677 nc->disabled_modules = 0x00000000;
678 nc->num_cpus = 2;
679 }
680
681 static const TypeInfo npcm7xx_soc_types[] = {
682 {
683 .name = TYPE_NPCM7XX,
684 .parent = TYPE_DEVICE,
685 .instance_size = sizeof(NPCM7xxState),
686 .instance_init = npcm7xx_init,
687 .class_size = sizeof(NPCM7xxClass),
688 .class_init = npcm7xx_class_init,
689 .abstract = true,
690 }, {
691 .name = TYPE_NPCM730,
692 .parent = TYPE_NPCM7XX,
693 .class_init = npcm730_class_init,
694 }, {
695 .name = TYPE_NPCM750,
696 .parent = TYPE_NPCM7XX,
697 .class_init = npcm750_class_init,
698 },
699 };
700
701 DEFINE_TYPES(npcm7xx_soc_types);
AR7 emulation for QEMU