2 * RISC-V Control and Status Registers.
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
26 /* CSR function table */
27 static riscv_csr_operations csr_ops
[];
29 /* CSR function table constants */
31 CSR_TABLE_SIZE
= 0x1000
34 /* CSR function table public API */
35 void riscv_get_csr_ops(int csrno
, riscv_csr_operations
*ops
)
37 *ops
= csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)];
40 void riscv_set_csr_ops(int csrno
, riscv_csr_operations
*ops
)
42 csr_ops
[csrno
& (CSR_TABLE_SIZE
- 1)] = *ops
;
46 static int fs(CPURISCVState
*env
, int csrno
)
48 #if !defined(CONFIG_USER_ONLY)
49 /* loose check condition for fcsr in vector extension */
50 if ((csrno
== CSR_FCSR
) && (env
->misa
& RVV
)) {
53 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
54 return -RISCV_EXCP_ILLEGAL_INST
;
60 static int vs(CPURISCVState
*env
, int csrno
)
62 if (env
->misa
& RVV
) {
68 static int ctr(CPURISCVState
*env
, int csrno
)
70 #if !defined(CONFIG_USER_ONLY)
71 CPUState
*cs
= env_cpu(env
);
72 RISCVCPU
*cpu
= RISCV_CPU(cs
);
74 if (!cpu
->cfg
.ext_counters
) {
75 /* The Counters extensions is not enabled */
76 return -RISCV_EXCP_ILLEGAL_INST
;
79 if (riscv_cpu_virt_enabled(env
)) {
82 if (!get_field(env
->hcounteren
, HCOUNTEREN_CY
) &&
83 get_field(env
->mcounteren
, HCOUNTEREN_CY
)) {
84 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
88 if (!get_field(env
->hcounteren
, HCOUNTEREN_TM
) &&
89 get_field(env
->mcounteren
, HCOUNTEREN_TM
)) {
90 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
94 if (!get_field(env
->hcounteren
, HCOUNTEREN_IR
) &&
95 get_field(env
->mcounteren
, HCOUNTEREN_IR
)) {
96 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
99 case CSR_HPMCOUNTER3
...CSR_HPMCOUNTER31
:
100 if (!get_field(env
->hcounteren
, 1 << (csrno
- CSR_HPMCOUNTER3
)) &&
101 get_field(env
->mcounteren
, 1 << (csrno
- CSR_HPMCOUNTER3
))) {
102 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
105 #if defined(TARGET_RISCV32)
107 if (!get_field(env
->hcounteren
, HCOUNTEREN_CY
) &&
108 get_field(env
->mcounteren
, HCOUNTEREN_CY
)) {
109 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
113 if (!get_field(env
->hcounteren
, HCOUNTEREN_TM
) &&
114 get_field(env
->mcounteren
, HCOUNTEREN_TM
)) {
115 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
119 if (!get_field(env
->hcounteren
, HCOUNTEREN_IR
) &&
120 get_field(env
->mcounteren
, HCOUNTEREN_IR
)) {
121 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
124 case CSR_HPMCOUNTER3H
...CSR_HPMCOUNTER31H
:
125 if (!get_field(env
->hcounteren
, 1 << (csrno
- CSR_HPMCOUNTER3H
)) &&
126 get_field(env
->mcounteren
, 1 << (csrno
- CSR_HPMCOUNTER3H
))) {
127 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
137 #if !defined(CONFIG_USER_ONLY)
138 static int any(CPURISCVState
*env
, int csrno
)
143 static int smode(CPURISCVState
*env
, int csrno
)
145 return -!riscv_has_ext(env
, RVS
);
148 static int hmode(CPURISCVState
*env
, int csrno
)
150 if (riscv_has_ext(env
, RVS
) &&
151 riscv_has_ext(env
, RVH
)) {
152 /* Hypervisor extension is supported */
153 if ((env
->priv
== PRV_S
&& !riscv_cpu_virt_enabled(env
)) ||
154 env
->priv
== PRV_M
) {
157 return -RISCV_EXCP_VIRT_INSTRUCTION_FAULT
;
161 return -RISCV_EXCP_ILLEGAL_INST
;
164 static int pmp(CPURISCVState
*env
, int csrno
)
166 return -!riscv_feature(env
, RISCV_FEATURE_PMP
);
170 /* User Floating-Point CSRs */
171 static int read_fflags(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
173 #if !defined(CONFIG_USER_ONLY)
174 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
175 return -RISCV_EXCP_ILLEGAL_INST
;
178 *val
= riscv_cpu_get_fflags(env
);
182 static int write_fflags(CPURISCVState
*env
, int csrno
, target_ulong val
)
184 #if !defined(CONFIG_USER_ONLY)
185 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
186 return -RISCV_EXCP_ILLEGAL_INST
;
188 env
->mstatus
|= MSTATUS_FS
;
190 riscv_cpu_set_fflags(env
, val
& (FSR_AEXC
>> FSR_AEXC_SHIFT
));
194 static int read_frm(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
196 #if !defined(CONFIG_USER_ONLY)
197 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
198 return -RISCV_EXCP_ILLEGAL_INST
;
205 static int write_frm(CPURISCVState
*env
, int csrno
, target_ulong val
)
207 #if !defined(CONFIG_USER_ONLY)
208 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
209 return -RISCV_EXCP_ILLEGAL_INST
;
211 env
->mstatus
|= MSTATUS_FS
;
213 env
->frm
= val
& (FSR_RD
>> FSR_RD_SHIFT
);
217 static int read_fcsr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
219 #if !defined(CONFIG_USER_ONLY)
220 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
221 return -RISCV_EXCP_ILLEGAL_INST
;
224 *val
= (riscv_cpu_get_fflags(env
) << FSR_AEXC_SHIFT
)
225 | (env
->frm
<< FSR_RD_SHIFT
);
226 if (vs(env
, csrno
) >= 0) {
227 *val
|= (env
->vxrm
<< FSR_VXRM_SHIFT
)
228 | (env
->vxsat
<< FSR_VXSAT_SHIFT
);
233 static int write_fcsr(CPURISCVState
*env
, int csrno
, target_ulong val
)
235 #if !defined(CONFIG_USER_ONLY)
236 if (!env
->debugger
&& !riscv_cpu_fp_enabled(env
)) {
237 return -RISCV_EXCP_ILLEGAL_INST
;
239 env
->mstatus
|= MSTATUS_FS
;
241 env
->frm
= (val
& FSR_RD
) >> FSR_RD_SHIFT
;
242 if (vs(env
, csrno
) >= 0) {
243 env
->vxrm
= (val
& FSR_VXRM
) >> FSR_VXRM_SHIFT
;
244 env
->vxsat
= (val
& FSR_VXSAT
) >> FSR_VXSAT_SHIFT
;
246 riscv_cpu_set_fflags(env
, (val
& FSR_AEXC
) >> FSR_AEXC_SHIFT
);
250 static int read_vtype(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
256 static int read_vl(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
262 static int read_vxrm(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
268 static int write_vxrm(CPURISCVState
*env
, int csrno
, target_ulong val
)
274 static int read_vxsat(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
280 static int write_vxsat(CPURISCVState
*env
, int csrno
, target_ulong val
)
286 static int read_vstart(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
292 static int write_vstart(CPURISCVState
*env
, int csrno
, target_ulong val
)
298 /* User Timers and Counters */
299 static int read_instret(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
301 #if !defined(CONFIG_USER_ONLY)
303 *val
= cpu_get_icount();
305 *val
= cpu_get_host_ticks();
308 *val
= cpu_get_host_ticks();
313 #if defined(TARGET_RISCV32)
314 static int read_instreth(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
316 #if !defined(CONFIG_USER_ONLY)
318 *val
= cpu_get_icount() >> 32;
320 *val
= cpu_get_host_ticks() >> 32;
323 *val
= cpu_get_host_ticks() >> 32;
327 #endif /* TARGET_RISCV32 */
329 #if defined(CONFIG_USER_ONLY)
330 static int read_time(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
332 *val
= cpu_get_host_ticks();
336 #if defined(TARGET_RISCV32)
337 static int read_timeh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
339 *val
= cpu_get_host_ticks() >> 32;
344 #else /* CONFIG_USER_ONLY */
346 static int read_time(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
348 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
350 if (!env
->rdtime_fn
) {
351 return -RISCV_EXCP_ILLEGAL_INST
;
354 *val
= env
->rdtime_fn() + delta
;
358 #if defined(TARGET_RISCV32)
359 static int read_timeh(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
361 uint64_t delta
= riscv_cpu_virt_enabled(env
) ? env
->htimedelta
: 0;
363 if (!env
->rdtime_fn
) {
364 return -RISCV_EXCP_ILLEGAL_INST
;
367 *val
= (env
->rdtime_fn() + delta
) >> 32;
372 /* Machine constants */
374 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
375 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
376 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
378 static const target_ulong delegable_ints
= S_MODE_INTERRUPTS
|
380 static const target_ulong all_ints
= M_MODE_INTERRUPTS
| S_MODE_INTERRUPTS
|
382 static const target_ulong delegable_excps
=
383 (1ULL << (RISCV_EXCP_INST_ADDR_MIS
)) |
384 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT
)) |
385 (1ULL << (RISCV_EXCP_ILLEGAL_INST
)) |
386 (1ULL << (RISCV_EXCP_BREAKPOINT
)) |
387 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS
)) |
388 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT
)) |
389 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS
)) |
390 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT
)) |
391 (1ULL << (RISCV_EXCP_U_ECALL
)) |
392 (1ULL << (RISCV_EXCP_S_ECALL
)) |
393 (1ULL << (RISCV_EXCP_VS_ECALL
)) |
394 (1ULL << (RISCV_EXCP_M_ECALL
)) |
395 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT
)) |
396 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT
)) |
397 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT
)) |
398 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT
)) |
399 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT
)) |
400 (1ULL << (RISCV_EXCP_VIRT_INSTRUCTION_FAULT
)) |
401 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT
));
402 static const target_ulong sstatus_v1_10_mask
= SSTATUS_SIE
| SSTATUS_SPIE
|
403 SSTATUS_UIE
| SSTATUS_UPIE
| SSTATUS_SPP
| SSTATUS_FS
| SSTATUS_XS
|
404 SSTATUS_SUM
| SSTATUS_MXR
| SSTATUS_SD
;
405 static const target_ulong sip_writable_mask
= SIP_SSIP
| MIP_USIP
| MIP_UEIP
;
406 static const target_ulong hip_writable_mask
= MIP_VSSIP
| MIP_VSTIP
| MIP_VSEIP
;
407 static const target_ulong vsip_writable_mask
= MIP_VSSIP
;
409 #if defined(TARGET_RISCV32)
410 static const char valid_vm_1_10
[16] = {
414 #elif defined(TARGET_RISCV64)
415 static const char valid_vm_1_10
[16] = {
421 #endif /* CONFIG_USER_ONLY */
423 /* Machine Information Registers */
424 static int read_zero(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
429 static int read_mhartid(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
435 /* Machine Trap Setup */
436 static int read_mstatus(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
442 static int validate_vm(CPURISCVState
*env
, target_ulong vm
)
444 return valid_vm_1_10
[vm
& 0xf];
447 static int write_mstatus(CPURISCVState
*env
, int csrno
, target_ulong val
)
449 target_ulong mstatus
= env
->mstatus
;
450 target_ulong mask
= 0;
453 /* flush tlb on mstatus fields that affect VM */
454 if ((val
^ mstatus
) & (MSTATUS_MXR
| MSTATUS_MPP
| MSTATUS_MPV
|
455 MSTATUS_MPRV
| MSTATUS_SUM
)) {
456 tlb_flush(env_cpu(env
));
458 mask
= MSTATUS_SIE
| MSTATUS_SPIE
| MSTATUS_MIE
| MSTATUS_MPIE
|
459 MSTATUS_SPP
| MSTATUS_FS
| MSTATUS_MPRV
| MSTATUS_SUM
|
460 MSTATUS_MPP
| MSTATUS_MXR
| MSTATUS_TVM
| MSTATUS_TSR
|
462 #if defined(TARGET_RISCV64)
464 * RV32: MPV and GVA are not in mstatus. The current plan is to
465 * add them to mstatush. For now, we just don't support it.
467 mask
|= MSTATUS_MPV
| MSTATUS_GVA
;
470 mstatus
= (mstatus
& ~mask
) | (val
& mask
);
472 dirty
= ((mstatus
& MSTATUS_FS
) == MSTATUS_FS
) |
473 ((mstatus
& MSTATUS_XS
) == MSTATUS_XS
);
474 mstatus
= set_field(mstatus
, MSTATUS_SD
, dirty
);
475 env
->mstatus
= mstatus
;
480 #ifdef TARGET_RISCV32
481 static int read_mstatush(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
483 *val
= env
->mstatush
;
487 static int write_mstatush(CPURISCVState
*env
, int csrno
, target_ulong val
)
489 if ((val
^ env
->mstatush
) & (MSTATUS_MPV
)) {
490 tlb_flush(env_cpu(env
));
493 val
&= MSTATUS_MPV
| MSTATUS_GVA
;
501 static int read_misa(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
507 static int write_misa(CPURISCVState
*env
, int csrno
, target_ulong val
)
509 if (!riscv_feature(env
, RISCV_FEATURE_MISA
)) {
510 /* drop write to misa */
514 /* 'I' or 'E' must be present */
515 if (!(val
& (RVI
| RVE
))) {
516 /* It is not, drop write to misa */
520 /* 'E' excludes all other extensions */
522 /* when we support 'E' we can do "val = RVE;" however
523 * for now we just drop writes if 'E' is present.
528 /* Mask extensions that are not supported by this hart */
529 val
&= env
->misa_mask
;
531 /* Mask extensions that are not supported by QEMU */
532 val
&= (RVI
| RVE
| RVM
| RVA
| RVF
| RVD
| RVC
| RVS
| RVU
);
534 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
535 if ((val
& RVD
) && !(val
& RVF
)) {
539 /* Suppress 'C' if next instruction is not aligned
540 * TODO: this should check next_pc
542 if ((val
& RVC
) && (GETPC() & ~3) != 0) {
546 /* misa.MXL writes are not supported by QEMU */
547 val
= (env
->misa
& MISA_MXL
) | (val
& ~MISA_MXL
);
549 /* flush translation cache */
550 if (val
!= env
->misa
) {
551 tb_flush(env_cpu(env
));
559 static int read_medeleg(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
565 static int write_medeleg(CPURISCVState
*env
, int csrno
, target_ulong val
)
567 env
->medeleg
= (env
->medeleg
& ~delegable_excps
) | (val
& delegable_excps
);
571 static int read_mideleg(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
577 static int write_mideleg(CPURISCVState
*env
, int csrno
, target_ulong val
)
579 env
->mideleg
= (env
->mideleg
& ~delegable_ints
) | (val
& delegable_ints
);
580 if (riscv_has_ext(env
, RVH
)) {
581 env
->mideleg
|= VS_MODE_INTERRUPTS
;
586 static int read_mie(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
592 static int write_mie(CPURISCVState
*env
, int csrno
, target_ulong val
)
594 env
->mie
= (env
->mie
& ~all_ints
) | (val
& all_ints
);
598 static int read_mtvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
604 static int write_mtvec(CPURISCVState
*env
, int csrno
, target_ulong val
)
606 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
610 qemu_log_mask(LOG_UNIMP
, "CSR_MTVEC: reserved mode not supported\n");
615 static int read_mcounteren(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
617 *val
= env
->mcounteren
;
621 static int write_mcounteren(CPURISCVState
*env
, int csrno
, target_ulong val
)
623 env
->mcounteren
= val
;
627 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
628 static int read_mscounteren(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
630 if (env
->priv_ver
< PRIV_VERSION_1_11_0
) {
631 return -RISCV_EXCP_ILLEGAL_INST
;
633 *val
= env
->mcounteren
;
637 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
638 static int write_mscounteren(CPURISCVState
*env
, int csrno
, target_ulong val
)
640 if (env
->priv_ver
< PRIV_VERSION_1_11_0
) {
641 return -RISCV_EXCP_ILLEGAL_INST
;
643 env
->mcounteren
= val
;
647 /* Machine Trap Handling */
648 static int read_mscratch(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
650 *val
= env
->mscratch
;
654 static int write_mscratch(CPURISCVState
*env
, int csrno
, target_ulong val
)
660 static int read_mepc(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
666 static int write_mepc(CPURISCVState
*env
, int csrno
, target_ulong val
)
672 static int read_mcause(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
678 static int write_mcause(CPURISCVState
*env
, int csrno
, target_ulong val
)
684 static int read_mbadaddr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
686 *val
= env
->mbadaddr
;
690 static int write_mbadaddr(CPURISCVState
*env
, int csrno
, target_ulong val
)
696 static int rmw_mip(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
697 target_ulong new_value
, target_ulong write_mask
)
699 RISCVCPU
*cpu
= env_archcpu(env
);
700 /* Allow software control of delegable interrupts not claimed by hardware */
701 target_ulong mask
= write_mask
& delegable_ints
& ~env
->miclaim
;
705 old_mip
= riscv_cpu_update_mip(cpu
, mask
, (new_value
& mask
));
711 *ret_value
= old_mip
;
717 /* Supervisor Trap Setup */
718 static int read_sstatus(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
720 target_ulong mask
= (sstatus_v1_10_mask
);
721 *val
= env
->mstatus
& mask
;
725 static int write_sstatus(CPURISCVState
*env
, int csrno
, target_ulong val
)
727 target_ulong mask
= (sstatus_v1_10_mask
);
728 target_ulong newval
= (env
->mstatus
& ~mask
) | (val
& mask
);
729 return write_mstatus(env
, CSR_MSTATUS
, newval
);
732 static int read_sie(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
734 if (riscv_cpu_virt_enabled(env
)) {
735 /* Tell the guest the VS bits, shifted to the S bit locations */
736 *val
= (env
->mie
& env
->mideleg
& VS_MODE_INTERRUPTS
) >> 1;
738 *val
= env
->mie
& env
->mideleg
;
743 static int write_sie(CPURISCVState
*env
, int csrno
, target_ulong val
)
747 if (riscv_cpu_virt_enabled(env
)) {
748 /* Shift the guests S bits to VS */
749 newval
= (env
->mie
& ~VS_MODE_INTERRUPTS
) |
750 ((val
<< 1) & VS_MODE_INTERRUPTS
);
752 newval
= (env
->mie
& ~S_MODE_INTERRUPTS
) | (val
& S_MODE_INTERRUPTS
);
755 return write_mie(env
, CSR_MIE
, newval
);
758 static int read_stvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
764 static int write_stvec(CPURISCVState
*env
, int csrno
, target_ulong val
)
766 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
770 qemu_log_mask(LOG_UNIMP
, "CSR_STVEC: reserved mode not supported\n");
775 static int read_scounteren(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
777 *val
= env
->scounteren
;
781 static int write_scounteren(CPURISCVState
*env
, int csrno
, target_ulong val
)
783 env
->scounteren
= val
;
787 /* Supervisor Trap Handling */
788 static int read_sscratch(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
790 *val
= env
->sscratch
;
794 static int write_sscratch(CPURISCVState
*env
, int csrno
, target_ulong val
)
800 static int read_sepc(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
806 static int write_sepc(CPURISCVState
*env
, int csrno
, target_ulong val
)
812 static int read_scause(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
818 static int write_scause(CPURISCVState
*env
, int csrno
, target_ulong val
)
824 static int read_sbadaddr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
826 *val
= env
->sbadaddr
;
830 static int write_sbadaddr(CPURISCVState
*env
, int csrno
, target_ulong val
)
836 static int rmw_sip(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
837 target_ulong new_value
, target_ulong write_mask
)
841 if (riscv_cpu_virt_enabled(env
)) {
842 /* Shift the new values to line up with the VS bits */
843 ret
= rmw_mip(env
, CSR_MSTATUS
, ret_value
, new_value
<< 1,
844 (write_mask
& sip_writable_mask
) << 1 & env
->mideleg
);
845 ret
&= vsip_writable_mask
;
848 ret
= rmw_mip(env
, CSR_MSTATUS
, ret_value
, new_value
,
849 write_mask
& env
->mideleg
& sip_writable_mask
);
852 *ret_value
&= env
->mideleg
;
856 /* Supervisor Protection and Translation */
857 static int read_satp(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
859 if (!riscv_feature(env
, RISCV_FEATURE_MMU
)) {
864 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
865 return -RISCV_EXCP_ILLEGAL_INST
;
873 static int write_satp(CPURISCVState
*env
, int csrno
, target_ulong val
)
875 if (!riscv_feature(env
, RISCV_FEATURE_MMU
)) {
878 if (validate_vm(env
, get_field(val
, SATP_MODE
)) &&
879 ((val
^ env
->satp
) & (SATP_MODE
| SATP_ASID
| SATP_PPN
)))
881 if (env
->priv
== PRV_S
&& get_field(env
->mstatus
, MSTATUS_TVM
)) {
882 return -RISCV_EXCP_ILLEGAL_INST
;
884 if((val
^ env
->satp
) & SATP_ASID
) {
885 tlb_flush(env_cpu(env
));
893 /* Hypervisor Extensions */
894 static int read_hstatus(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
897 #ifdef TARGET_RISCV64
898 /* We only support 64-bit VSXL */
899 *val
= set_field(*val
, HSTATUS_VSXL
, 2);
901 /* We only support little endian */
902 *val
= set_field(*val
, HSTATUS_VSBE
, 0);
906 static int write_hstatus(CPURISCVState
*env
, int csrno
, target_ulong val
)
909 #ifdef TARGET_RISCV64
910 if (get_field(val
, HSTATUS_VSXL
) != 2) {
911 qemu_log_mask(LOG_UNIMP
, "QEMU does not support mixed HSXLEN options.");
914 if (get_field(val
, HSTATUS_VSBE
) != 0) {
915 qemu_log_mask(LOG_UNIMP
, "QEMU does not support big endian guests.");
920 static int read_hedeleg(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
926 static int write_hedeleg(CPURISCVState
*env
, int csrno
, target_ulong val
)
932 static int read_hideleg(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
938 static int write_hideleg(CPURISCVState
*env
, int csrno
, target_ulong val
)
944 static int rmw_hvip(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
945 target_ulong new_value
, target_ulong write_mask
)
947 int ret
= rmw_mip(env
, 0, ret_value
, new_value
,
948 write_mask
& hip_writable_mask
);
950 *ret_value
&= hip_writable_mask
;
955 static int rmw_hip(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
956 target_ulong new_value
, target_ulong write_mask
)
958 int ret
= rmw_mip(env
, 0, ret_value
, new_value
,
959 write_mask
& hip_writable_mask
);
961 *ret_value
&= hip_writable_mask
;
966 static int read_hie(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
968 *val
= env
->mie
& VS_MODE_INTERRUPTS
;
972 static int write_hie(CPURISCVState
*env
, int csrno
, target_ulong val
)
974 target_ulong newval
= (env
->mie
& ~VS_MODE_INTERRUPTS
) | (val
& VS_MODE_INTERRUPTS
);
975 return write_mie(env
, CSR_MIE
, newval
);
978 static int read_hcounteren(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
980 *val
= env
->hcounteren
;
984 static int write_hcounteren(CPURISCVState
*env
, int csrno
, target_ulong val
)
986 env
->hcounteren
= val
;
990 static int read_hgeie(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
992 qemu_log_mask(LOG_UNIMP
, "No support for a non-zero GEILEN.");
996 static int write_hgeie(CPURISCVState
*env
, int csrno
, target_ulong val
)
998 qemu_log_mask(LOG_UNIMP
, "No support for a non-zero GEILEN.");
1002 static int read_htval(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1008 static int write_htval(CPURISCVState
*env
, int csrno
, target_ulong val
)
1014 static int read_htinst(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1020 static int write_htinst(CPURISCVState
*env
, int csrno
, target_ulong val
)
1025 static int read_hgeip(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1027 qemu_log_mask(LOG_UNIMP
, "No support for a non-zero GEILEN.");
1031 static int write_hgeip(CPURISCVState
*env
, int csrno
, target_ulong val
)
1033 qemu_log_mask(LOG_UNIMP
, "No support for a non-zero GEILEN.");
1037 static int read_hgatp(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1043 static int write_hgatp(CPURISCVState
*env
, int csrno
, target_ulong val
)
1049 static int read_htimedelta(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1051 if (!env
->rdtime_fn
) {
1052 return -RISCV_EXCP_ILLEGAL_INST
;
1055 #if defined(TARGET_RISCV32)
1056 *val
= env
->htimedelta
& 0xffffffff;
1058 *val
= env
->htimedelta
;
1063 static int write_htimedelta(CPURISCVState
*env
, int csrno
, target_ulong val
)
1065 if (!env
->rdtime_fn
) {
1066 return -RISCV_EXCP_ILLEGAL_INST
;
1069 #if defined(TARGET_RISCV32)
1070 env
->htimedelta
= deposit64(env
->htimedelta
, 0, 32, (uint64_t)val
);
1072 env
->htimedelta
= val
;
1077 #if defined(TARGET_RISCV32)
1078 static int read_htimedeltah(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1080 if (!env
->rdtime_fn
) {
1081 return -RISCV_EXCP_ILLEGAL_INST
;
1084 *val
= env
->htimedelta
>> 32;
1088 static int write_htimedeltah(CPURISCVState
*env
, int csrno
, target_ulong val
)
1090 if (!env
->rdtime_fn
) {
1091 return -RISCV_EXCP_ILLEGAL_INST
;
1094 env
->htimedelta
= deposit64(env
->htimedelta
, 32, 32, (uint64_t)val
);
1099 /* Virtual CSR Registers */
1100 static int read_vsstatus(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1102 *val
= env
->vsstatus
;
1106 static int write_vsstatus(CPURISCVState
*env
, int csrno
, target_ulong val
)
1108 env
->vsstatus
= val
;
1112 static int rmw_vsip(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
1113 target_ulong new_value
, target_ulong write_mask
)
1115 int ret
= rmw_mip(env
, 0, ret_value
, new_value
,
1116 write_mask
& env
->mideleg
& vsip_writable_mask
);
1120 static int read_vsie(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1122 *val
= env
->mie
& env
->mideleg
& VS_MODE_INTERRUPTS
;
1126 static int write_vsie(CPURISCVState
*env
, int csrno
, target_ulong val
)
1128 target_ulong newval
= (env
->mie
& ~env
->mideleg
) | (val
& env
->mideleg
& MIP_VSSIP
);
1129 return write_mie(env
, CSR_MIE
, newval
);
1132 static int read_vstvec(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1138 static int write_vstvec(CPURISCVState
*env
, int csrno
, target_ulong val
)
1144 static int read_vsscratch(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1146 *val
= env
->vsscratch
;
1150 static int write_vsscratch(CPURISCVState
*env
, int csrno
, target_ulong val
)
1152 env
->vsscratch
= val
;
1156 static int read_vsepc(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1162 static int write_vsepc(CPURISCVState
*env
, int csrno
, target_ulong val
)
1168 static int read_vscause(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1170 *val
= env
->vscause
;
1174 static int write_vscause(CPURISCVState
*env
, int csrno
, target_ulong val
)
1180 static int read_vstval(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1186 static int write_vstval(CPURISCVState
*env
, int csrno
, target_ulong val
)
1192 static int read_vsatp(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1198 static int write_vsatp(CPURISCVState
*env
, int csrno
, target_ulong val
)
1204 static int read_mtval2(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1210 static int write_mtval2(CPURISCVState
*env
, int csrno
, target_ulong val
)
1216 static int read_mtinst(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1222 static int write_mtinst(CPURISCVState
*env
, int csrno
, target_ulong val
)
1228 /* Physical Memory Protection */
1229 static int read_pmpcfg(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1231 *val
= pmpcfg_csr_read(env
, csrno
- CSR_PMPCFG0
);
1235 static int write_pmpcfg(CPURISCVState
*env
, int csrno
, target_ulong val
)
1237 pmpcfg_csr_write(env
, csrno
- CSR_PMPCFG0
, val
);
1241 static int read_pmpaddr(CPURISCVState
*env
, int csrno
, target_ulong
*val
)
1243 *val
= pmpaddr_csr_read(env
, csrno
- CSR_PMPADDR0
);
1247 static int write_pmpaddr(CPURISCVState
*env
, int csrno
, target_ulong val
)
1249 pmpaddr_csr_write(env
, csrno
- CSR_PMPADDR0
, val
);
1256 * riscv_csrrw - read and/or update control and status register
1258 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
1259 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
1260 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
1261 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
1264 int riscv_csrrw(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
1265 target_ulong new_value
, target_ulong write_mask
)
1268 target_ulong old_value
;
1269 RISCVCPU
*cpu
= env_archcpu(env
);
1271 /* check privileges and return -1 if check fails */
1272 #if !defined(CONFIG_USER_ONLY)
1273 int effective_priv
= env
->priv
;
1274 int read_only
= get_field(csrno
, 0xC00) == 3;
1276 if (riscv_has_ext(env
, RVH
) &&
1277 env
->priv
== PRV_S
&&
1278 !riscv_cpu_virt_enabled(env
)) {
1280 * We are in S mode without virtualisation, therefore we are in HS Mode.
1281 * Add 1 to the effective privledge level to allow us to access the
1287 if ((write_mask
&& read_only
) ||
1288 (!env
->debugger
&& (effective_priv
< get_field(csrno
, 0x300)))) {
1289 return -RISCV_EXCP_ILLEGAL_INST
;
1293 /* ensure the CSR extension is enabled. */
1294 if (!cpu
->cfg
.ext_icsr
) {
1295 return -RISCV_EXCP_ILLEGAL_INST
;
1298 /* check predicate */
1299 if (!csr_ops
[csrno
].predicate
) {
1300 return -RISCV_EXCP_ILLEGAL_INST
;
1302 ret
= csr_ops
[csrno
].predicate(env
, csrno
);
1307 /* execute combined read/write operation if it exists */
1308 if (csr_ops
[csrno
].op
) {
1309 return csr_ops
[csrno
].op(env
, csrno
, ret_value
, new_value
, write_mask
);
1312 /* if no accessor exists then return failure */
1313 if (!csr_ops
[csrno
].read
) {
1314 return -RISCV_EXCP_ILLEGAL_INST
;
1317 /* read old value */
1318 ret
= csr_ops
[csrno
].read(env
, csrno
, &old_value
);
1323 /* write value if writable and write mask set, otherwise drop writes */
1325 new_value
= (old_value
& ~write_mask
) | (new_value
& write_mask
);
1326 if (csr_ops
[csrno
].write
) {
1327 ret
= csr_ops
[csrno
].write(env
, csrno
, new_value
);
1334 /* return old value */
1336 *ret_value
= old_value
;
1343 * Debugger support. If not in user mode, set env->debugger before the
1344 * riscv_csrrw call and clear it after the call.
1346 int riscv_csrrw_debug(CPURISCVState
*env
, int csrno
, target_ulong
*ret_value
,
1347 target_ulong new_value
, target_ulong write_mask
)
1350 #if !defined(CONFIG_USER_ONLY)
1351 env
->debugger
= true;
1353 ret
= riscv_csrrw(env
, csrno
, ret_value
, new_value
, write_mask
);
1354 #if !defined(CONFIG_USER_ONLY)
1355 env
->debugger
= false;
1360 /* Control and Status Register function table */
1361 static riscv_csr_operations csr_ops
[CSR_TABLE_SIZE
] = {
1362 /* User Floating-Point CSRs */
1363 [CSR_FFLAGS
] = { fs
, read_fflags
, write_fflags
},
1364 [CSR_FRM
] = { fs
, read_frm
, write_frm
},
1365 [CSR_FCSR
] = { fs
, read_fcsr
, write_fcsr
},
1367 [CSR_VSTART
] = { vs
, read_vstart
, write_vstart
},
1368 [CSR_VXSAT
] = { vs
, read_vxsat
, write_vxsat
},
1369 [CSR_VXRM
] = { vs
, read_vxrm
, write_vxrm
},
1370 [CSR_VL
] = { vs
, read_vl
},
1371 [CSR_VTYPE
] = { vs
, read_vtype
},
1372 /* User Timers and Counters */
1373 [CSR_CYCLE
] = { ctr
, read_instret
},
1374 [CSR_INSTRET
] = { ctr
, read_instret
},
1375 #if defined(TARGET_RISCV32)
1376 [CSR_CYCLEH
] = { ctr
, read_instreth
},
1377 [CSR_INSTRETH
] = { ctr
, read_instreth
},
1380 /* In privileged mode, the monitor will have to emulate TIME CSRs only if
1381 * rdtime callback is not provided by machine/platform emulation */
1382 [CSR_TIME
] = { ctr
, read_time
},
1383 #if defined(TARGET_RISCV32)
1384 [CSR_TIMEH
] = { ctr
, read_timeh
},
1387 #if !defined(CONFIG_USER_ONLY)
1388 /* Machine Timers and Counters */
1389 [CSR_MCYCLE
] = { any
, read_instret
},
1390 [CSR_MINSTRET
] = { any
, read_instret
},
1391 #if defined(TARGET_RISCV32)
1392 [CSR_MCYCLEH
] = { any
, read_instreth
},
1393 [CSR_MINSTRETH
] = { any
, read_instreth
},
1396 /* Machine Information Registers */
1397 [CSR_MVENDORID
] = { any
, read_zero
},
1398 [CSR_MARCHID
] = { any
, read_zero
},
1399 [CSR_MIMPID
] = { any
, read_zero
},
1400 [CSR_MHARTID
] = { any
, read_mhartid
},
1402 /* Machine Trap Setup */
1403 [CSR_MSTATUS
] = { any
, read_mstatus
, write_mstatus
},
1404 [CSR_MISA
] = { any
, read_misa
, write_misa
},
1405 [CSR_MIDELEG
] = { any
, read_mideleg
, write_mideleg
},
1406 [CSR_MEDELEG
] = { any
, read_medeleg
, write_medeleg
},
1407 [CSR_MIE
] = { any
, read_mie
, write_mie
},
1408 [CSR_MTVEC
] = { any
, read_mtvec
, write_mtvec
},
1409 [CSR_MCOUNTEREN
] = { any
, read_mcounteren
, write_mcounteren
},
1411 #if defined(TARGET_RISCV32)
1412 [CSR_MSTATUSH
] = { any
, read_mstatush
, write_mstatush
},
1415 [CSR_MSCOUNTEREN
] = { any
, read_mscounteren
, write_mscounteren
},
1417 /* Machine Trap Handling */
1418 [CSR_MSCRATCH
] = { any
, read_mscratch
, write_mscratch
},
1419 [CSR_MEPC
] = { any
, read_mepc
, write_mepc
},
1420 [CSR_MCAUSE
] = { any
, read_mcause
, write_mcause
},
1421 [CSR_MBADADDR
] = { any
, read_mbadaddr
, write_mbadaddr
},
1422 [CSR_MIP
] = { any
, NULL
, NULL
, rmw_mip
},
1424 /* Supervisor Trap Setup */
1425 [CSR_SSTATUS
] = { smode
, read_sstatus
, write_sstatus
},
1426 [CSR_SIE
] = { smode
, read_sie
, write_sie
},
1427 [CSR_STVEC
] = { smode
, read_stvec
, write_stvec
},
1428 [CSR_SCOUNTEREN
] = { smode
, read_scounteren
, write_scounteren
},
1430 /* Supervisor Trap Handling */
1431 [CSR_SSCRATCH
] = { smode
, read_sscratch
, write_sscratch
},
1432 [CSR_SEPC
] = { smode
, read_sepc
, write_sepc
},
1433 [CSR_SCAUSE
] = { smode
, read_scause
, write_scause
},
1434 [CSR_SBADADDR
] = { smode
, read_sbadaddr
, write_sbadaddr
},
1435 [CSR_SIP
] = { smode
, NULL
, NULL
, rmw_sip
},
1437 /* Supervisor Protection and Translation */
1438 [CSR_SATP
] = { smode
, read_satp
, write_satp
},
1440 [CSR_HSTATUS
] = { hmode
, read_hstatus
, write_hstatus
},
1441 [CSR_HEDELEG
] = { hmode
, read_hedeleg
, write_hedeleg
},
1442 [CSR_HIDELEG
] = { hmode
, read_hideleg
, write_hideleg
},
1443 [CSR_HVIP
] = { hmode
, NULL
, NULL
, rmw_hvip
},
1444 [CSR_HIP
] = { hmode
, NULL
, NULL
, rmw_hip
},
1445 [CSR_HIE
] = { hmode
, read_hie
, write_hie
},
1446 [CSR_HCOUNTEREN
] = { hmode
, read_hcounteren
, write_hcounteren
},
1447 [CSR_HGEIE
] = { hmode
, read_hgeie
, write_hgeie
},
1448 [CSR_HTVAL
] = { hmode
, read_htval
, write_htval
},
1449 [CSR_HTINST
] = { hmode
, read_htinst
, write_htinst
},
1450 [CSR_HGEIP
] = { hmode
, read_hgeip
, write_hgeip
},
1451 [CSR_HGATP
] = { hmode
, read_hgatp
, write_hgatp
},
1452 [CSR_HTIMEDELTA
] = { hmode
, read_htimedelta
, write_htimedelta
},
1453 #if defined(TARGET_RISCV32)
1454 [CSR_HTIMEDELTAH
] = { hmode
, read_htimedeltah
, write_htimedeltah
},
1457 [CSR_VSSTATUS
] = { hmode
, read_vsstatus
, write_vsstatus
},
1458 [CSR_VSIP
] = { hmode
, NULL
, NULL
, rmw_vsip
},
1459 [CSR_VSIE
] = { hmode
, read_vsie
, write_vsie
},
1460 [CSR_VSTVEC
] = { hmode
, read_vstvec
, write_vstvec
},
1461 [CSR_VSSCRATCH
] = { hmode
, read_vsscratch
, write_vsscratch
},
1462 [CSR_VSEPC
] = { hmode
, read_vsepc
, write_vsepc
},
1463 [CSR_VSCAUSE
] = { hmode
, read_vscause
, write_vscause
},
1464 [CSR_VSTVAL
] = { hmode
, read_vstval
, write_vstval
},
1465 [CSR_VSATP
] = { hmode
, read_vsatp
, write_vsatp
},
1467 [CSR_MTVAL2
] = { hmode
, read_mtval2
, write_mtval2
},
1468 [CSR_MTINST
] = { hmode
, read_mtinst
, write_mtinst
},
1470 /* Physical Memory Protection */
1471 [CSR_PMPCFG0
... CSR_PMPCFG3
] = { pmp
, read_pmpcfg
, write_pmpcfg
},
1472 [CSR_PMPADDR0
... CSR_PMPADDR15
] = { pmp
, read_pmpaddr
, write_pmpaddr
},
1474 /* Performance Counters */
1475 [CSR_HPMCOUNTER3
... CSR_HPMCOUNTER31
] = { ctr
, read_zero
},
1476 [CSR_MHPMCOUNTER3
... CSR_MHPMCOUNTER31
] = { any
, read_zero
},
1477 [CSR_MHPMEVENT3
... CSR_MHPMEVENT31
] = { any
, read_zero
},
1478 #if defined(TARGET_RISCV32)
1479 [CSR_HPMCOUNTER3H
... CSR_HPMCOUNTER31H
] = { ctr
, read_zero
},
1480 [CSR_MHPMCOUNTER3H
... CSR_MHPMCOUNTER31H
] = { any
, read_zero
},
1482 #endif /* !CONFIG_USER_ONLY */