| commit | d9f4bb27dbff2e40ec2e36eb8017c9dedce77f30 | |
| author | Andre Przywara <andre.przywara@amd.com> | |
| Fri, 18 Sep 2009 22:30:48 +0000 (19 00:30 +0200) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Sun, 4 Oct 2009 12:09:41 +0000 (4 14:09 +0200) | ||
| tree | 60e4374cd0a5fd95cfadb397f0413468d11a1f14 | treesnapshot (tar.gz zip) |
| parent | ccd59d09a9d0c75b86185b89d8246e40b5f01168 | commitdiff |
target-i386: add SSE4a instruction support
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This adds support for the AMD Phenom/Barcelona's SSE4a instructions.
Those include insertq and extrq, which are doing shift and mask on
XMM registers, in two versions (immediate shift/length values and
stored in another XMM register).
Additionally it implements movntss, movntsd, which are scalar
non-temporal stores (avoiding cache trashing). These are implemented
as normal stores, though.
SSE4a is guarded by the SSE4A CPUID bit (Fn8000_0001:ECX[6]).
Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target-i386/ops_sse.h | diffblobblamehistory | |
| target-i386/ops_sse_header.h | diffblobblamehistory | |
| target-i386/translate.c | diffblobblamehistory |