2 * QEMU PowerPC E500 embedded processors pci controller emulation
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
6 * Author: Yu Liu, <yu.liu@freescale.com>
8 * This file is derived from hw/ppc4xx_pci.c,
9 * the copyright for that material belongs to the original owners.
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
26 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
28 #define pci_debug(fmt, ...)
31 #define PCIE500_CFGADDR 0x0
32 #define PCIE500_CFGDATA 0x4
33 #define PCIE500_REG_BASE 0xC00
34 #define PCIE500_REG_SIZE (0x1000 - PCIE500_REG_BASE)
36 #define PPCE500_PCI_CONFIG_ADDR 0x0
37 #define PPCE500_PCI_CONFIG_DATA 0x4
38 #define PPCE500_PCI_INTACK 0x8
40 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
41 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
42 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
43 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
44 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
45 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
46 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
48 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
51 #define PCI_POTEAR 0x4
52 #define PCI_POWBAR 0x8
53 #define PCI_POWAR 0x10
56 #define PCI_PIWBAR 0x8
57 #define PCI_PIWBEAR 0xC
58 #define PCI_PIWAR 0x10
60 #define PPCE500_PCI_NR_POBS 5
61 #define PPCE500_PCI_NR_PIBS 3
77 struct PPCE500PCIState
{
78 struct pci_outbound pob
[PPCE500_PCI_NR_POBS
];
79 struct pci_inbound pib
[PPCE500_PCI_NR_PIBS
];
81 PCIHostState pci_state
;
85 typedef struct PPCE500PCIState PPCE500PCIState
;
87 static uint32_t pci_reg_read4(void *opaque
, target_phys_addr_t addr
)
89 PPCE500PCIState
*pci
= opaque
;
100 switch (addr
& 0xC) {
101 case PCI_POTAR
: value
= pci
->pob
[(addr
>> 5) & 0x7].potar
; break;
102 case PCI_POTEAR
: value
= pci
->pob
[(addr
>> 5) & 0x7].potear
; break;
103 case PCI_POWBAR
: value
= pci
->pob
[(addr
>> 5) & 0x7].powbar
; break;
104 case PCI_POWAR
: value
= pci
->pob
[(addr
>> 5) & 0x7].powar
; break;
109 case PPCE500_PCI_IW3
:
110 case PPCE500_PCI_IW2
:
111 case PPCE500_PCI_IW1
:
112 switch (addr
& 0xC) {
113 case PCI_PITAR
: value
= pci
->pib
[(addr
>> 5) & 0x3].pitar
; break;
114 case PCI_PIWBAR
: value
= pci
->pib
[(addr
>> 5) & 0x3].piwbar
; break;
115 case PCI_PIWBEAR
: value
= pci
->pib
[(addr
>> 5) & 0x3].piwbear
; break;
116 case PCI_PIWAR
: value
= pci
->pib
[(addr
>> 5) & 0x3].piwar
; break;
121 case PPCE500_PCI_GASKET_TIMR
:
122 value
= pci
->gasket_time
;
129 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx
") -> value:%x\n", __func__
,
134 static CPUReadMemoryFunc
* const e500_pci_reg_read
[] = {
140 static void pci_reg_write4(void *opaque
, target_phys_addr_t addr
,
143 PPCE500PCIState
*pci
= opaque
;
148 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx
")\n",
149 __func__
, value
, win
, addr
);
152 case PPCE500_PCI_OW1
:
153 case PPCE500_PCI_OW2
:
154 case PPCE500_PCI_OW3
:
155 case PPCE500_PCI_OW4
:
156 switch (addr
& 0xC) {
157 case PCI_POTAR
: pci
->pob
[(addr
>> 5) & 0x7].potar
= value
; break;
158 case PCI_POTEAR
: pci
->pob
[(addr
>> 5) & 0x7].potear
= value
; break;
159 case PCI_POWBAR
: pci
->pob
[(addr
>> 5) & 0x7].powbar
= value
; break;
160 case PCI_POWAR
: pci
->pob
[(addr
>> 5) & 0x7].powar
= value
; break;
165 case PPCE500_PCI_IW3
:
166 case PPCE500_PCI_IW2
:
167 case PPCE500_PCI_IW1
:
168 switch (addr
& 0xC) {
169 case PCI_PITAR
: pci
->pib
[(addr
>> 5) & 0x3].pitar
= value
; break;
170 case PCI_PIWBAR
: pci
->pib
[(addr
>> 5) & 0x3].piwbar
= value
; break;
171 case PCI_PIWBEAR
: pci
->pib
[(addr
>> 5) & 0x3].piwbear
= value
; break;
172 case PCI_PIWAR
: pci
->pib
[(addr
>> 5) & 0x3].piwar
= value
; break;
177 case PPCE500_PCI_GASKET_TIMR
:
178 pci
->gasket_time
= value
;
186 static CPUWriteMemoryFunc
* const e500_pci_reg_write
[] = {
192 static int mpc85xx_pci_map_irq(PCIDevice
*pci_dev
, int irq_num
)
194 int devno
= pci_dev
->devfn
>> 3, ret
= 0;
200 ret
= (irq_num
+ devno
- 0x10) % 4;
203 printf("Error:%s:unknow dev number\n", __func__
);
206 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__
,
207 pci_dev
->devfn
, irq_num
, ret
, devno
);
212 static void mpc85xx_pci_set_irq(void *opaque
, int irq_num
, int level
)
214 qemu_irq
*pic
= opaque
;
216 pci_debug("%s: PCI irq %d, level:%d\n", __func__
, irq_num
, level
);
218 qemu_set_irq(pic
[irq_num
], level
);
221 static void ppce500_pci_save(QEMUFile
*f
, void *opaque
)
223 PPCE500PCIState
*controller
= opaque
;
226 pci_device_save(controller
->pci_dev
, f
);
228 for (i
= 0; i
< PPCE500_PCI_NR_POBS
; i
++) {
229 qemu_put_be32s(f
, &controller
->pob
[i
].potar
);
230 qemu_put_be32s(f
, &controller
->pob
[i
].potear
);
231 qemu_put_be32s(f
, &controller
->pob
[i
].powbar
);
232 qemu_put_be32s(f
, &controller
->pob
[i
].powar
);
235 for (i
= 0; i
< PPCE500_PCI_NR_PIBS
; i
++) {
236 qemu_put_be32s(f
, &controller
->pib
[i
].pitar
);
237 qemu_put_be32s(f
, &controller
->pib
[i
].piwbar
);
238 qemu_put_be32s(f
, &controller
->pib
[i
].piwbear
);
239 qemu_put_be32s(f
, &controller
->pib
[i
].piwar
);
241 qemu_put_be32s(f
, &controller
->gasket_time
);
244 static int ppce500_pci_load(QEMUFile
*f
, void *opaque
, int version_id
)
246 PPCE500PCIState
*controller
= opaque
;
252 pci_device_load(controller
->pci_dev
, f
);
254 for (i
= 0; i
< PPCE500_PCI_NR_POBS
; i
++) {
255 qemu_get_be32s(f
, &controller
->pob
[i
].potar
);
256 qemu_get_be32s(f
, &controller
->pob
[i
].potear
);
257 qemu_get_be32s(f
, &controller
->pob
[i
].powbar
);
258 qemu_get_be32s(f
, &controller
->pob
[i
].powar
);
261 for (i
= 0; i
< PPCE500_PCI_NR_PIBS
; i
++) {
262 qemu_get_be32s(f
, &controller
->pib
[i
].pitar
);
263 qemu_get_be32s(f
, &controller
->pib
[i
].piwbar
);
264 qemu_get_be32s(f
, &controller
->pib
[i
].piwbear
);
265 qemu_get_be32s(f
, &controller
->pib
[i
].piwar
);
267 qemu_get_be32s(f
, &controller
->gasket_time
);
272 PCIBus
*ppce500_pci_init(qemu_irq pci_irqs
[4], target_phys_addr_t registers
)
274 PPCE500PCIState
*controller
;
277 static int ppce500_pci_id
;
279 controller
= qemu_mallocz(sizeof(PPCE500PCIState
));
281 controller
->pci_state
.bus
= pci_register_bus(NULL
, "pci",
285 d
= pci_register_device(controller
->pci_state
.bus
,
286 "host bridge", sizeof(PCIDevice
),
289 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_FREESCALE
);
290 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_MPC8533E
);
291 pci_config_set_class(d
->config
, PCI_CLASS_PROCESSOR_POWERPC
);
293 controller
->pci_dev
= d
;
296 index
= pci_host_config_register_io_memory_noswap(&controller
->pci_state
);
299 cpu_register_physical_memory(registers
+ PCIE500_CFGADDR
, 4, index
);
302 index
= pci_host_data_register_io_memory(&controller
->pci_state
);
305 cpu_register_physical_memory(registers
+ PCIE500_CFGDATA
, 4, index
);
307 index
= cpu_register_io_memory(e500_pci_reg_read
,
308 e500_pci_reg_write
, controller
);
311 cpu_register_physical_memory(registers
+ PCIE500_REG_BASE
,
312 PCIE500_REG_SIZE
, index
);
314 /* XXX load/save code not tested. */
315 register_savevm("ppce500_pci", ppce500_pci_id
++, 1,
316 ppce500_pci_save
, ppce500_pci_load
, controller
);
318 return controller
->pci_state
.bus
;
321 printf("%s error\n", __func__
);
322 qemu_free(controller
);