| commit | 98538d9eab04c57540a95df7918851cf8c2f360f | |
| author | Alexander Graf <agraf@suse.de> | |
| Wed, 1 May 2013 22:27:51 +0000 (2 00:27 +0200) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Mon, 6 May 2013 15:17:00 +0000 (6 17:17 +0200) | ||
| tree | 8ee28e728ce219634d39a8a439c27fdba5174777 | treesnapshot (tar.gz zip) |
| parent | 5a8f4e84c42350265c0953eef0d41cb8d250aef3 | commitdiff |
PPC: Add MMU type for 2.06 with AMR but no TB pages
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB
MMU capability from the MMU type mask, but not the AMR bit.
This leads to us having a new MMU type that we don't check for in our
MMU management functions.
Add the new type, so that we don't have to worry about breakage there.
We're not going to use the TCG MMU management in that case anyway.
The long term fix for this will be to move all these MMU management
functions to class callbacks.
Signed-off-by: Alexander Graf <agraf@suse.de>
When running -cpu on a POWER7 system with PR KVM, we mask out the 1TB
MMU capability from the MMU type mask, but not the AMR bit.
This leads to us having a new MMU type that we don't check for in our
MMU management functions.
Add the new type, so that we don't have to worry about breakage there.
We're not going to use the TCG MMU management in that case anyway.
The long term fix for this will be to move all these MMU management
functions to class callbacks.
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/cpu.h | diffblobblamehistory | |
| target-ppc/mmu_helper.c | diffblobblamehistory |