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2019-10-28	Alistair Francis	riscv/sifive_u: Add the start-in-flash property Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Manually define the machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add QSPI memory region Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-10-28	Alistair Francis	riscv/sifive_u: Add L2-LIM cache memory Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Use TB_FLAGS_MSTATUS_FS for floating... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Fix mstatus dirty mask Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Update the Hypervisor CSRs to v0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	target/riscv: Create function to test if FP is enabled Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-09-17	Alistair Francis	riscv: plic: Remove unused interrupt functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-26	Alistair Francis	riscv/boot: Fixup the RISC-V firmware warning Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	hw/riscv: Load OpenSBI as the default firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-18	Alistair Francis	roms: Add OpenSBI version 0.4 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-07-09	Alistair Francis	tcg/riscv: Fix RISC-VH host build failure Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Extend the kernel loading support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Add support for loading a firmware Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-27	Alistair Francis	hw/riscv: Split out the boot functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add support for disabling/enabling Counters Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Remove user version information Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Require either I or E base extension Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	qemu-deprecated.texi: Deprecate the RISC-V privledge... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Set privledge spec 1.11.0 as default Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-25	Alistair Francis	target/riscv: Add the mcountinhibit CSR Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Add the privledge spec version 1.11.0 Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Restructure deprecatd CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-06-24	Alistair Francis	target/riscv: Allow setting ISA extensions via CPU... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the HGATP register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the HSTATUS register masks Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add Hypervisor CSR macros Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Allow setting mstatus virtulisation bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add the MPV and MTL mstatus bits Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Improve the scause logic Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Trigger interrupt on MIP update asynchronously Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Mark privilege level 2 as reserved Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	riscv: spike: Add a generic spike machine Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Deprecate the generic no MMU CPUs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Add a base 32 and 64 bit CPU Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	target/riscv: Create settable CPU properties Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	riscv: virt: Allow specifying a CPU via commandline Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-24	Alistair Francis	linux-user/riscv: Add the CPU type as a comment Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-23	Alistair Francis	target/arm: Fix vector operation segfault Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-05-09	Alistair Francis	linux-user/elfload: Fix GCC 9 build warnings Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-04-04	Alistair Francis	riscv: plic: Log guest errors Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-04-04	Alistair Francis	riscv: plic: Fix incorrect irq calculation Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-03-27	Alistair Francis	MAINTAINERS: Update the device tree maintainers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-03-19	Alistair Francis	target/riscv: Remove unused struct Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-03-19	Alistair Francis	riscv: sifive_u: Allow up to 4 CPUs to be created Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-03-19	Alistair Francis	riscv: pmp: Log pmp access errors as guest errors Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-03-18	Alistair Francis	riscv: plic: Set msi_nonbroken as true Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-02-11	Alistair Francis	riscv: Ensure the kernel start address is correctly... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-02-11	Alistair Francis	RISC-V: Add priv_ver to DisasContext Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2019-01-10	Alistair Francis	default-configs: Enable USB support for RISC-V machines Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	configure: Add support for building RISC-V host Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	disas: Add RISC-V support Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg: Add RISC-V cpu signal handler Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the target init code Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the prologue generation and register... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the out op decoder Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add direct load and store instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add slowpath load and store instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add branch and jump instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the add2 and sub2 instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the out load and store instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the extract instructions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the mov and movi instruction Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the relocation functions Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the instruction emitters Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the immediate encoders Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add support for the constraints Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the tcg target registers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	tcg/riscv: Add the tcg-target.h file Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	exec: Add RISC-V GCC poison macro Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	linux-user: Add host dependency for RISC-V 64-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	linux-user: Add host dependency for RISC-V 32-bit Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-25	Alistair Francis	elf.h: Add the RISCV ELF magic numbers Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-20	Alistair Francis	riscv: Enable VGA and PCIE_VGA Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-20	Alistair Francis	hw/riscv/virt: Connect the gpex PCIe Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-20	Alistair Francis	hw/riscv/virt: Adjust memory layout spacing Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-20	Alistair Francis	hw/riscv/virt: Increase the number of interrupts Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-12-17	Alistair Francis	tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_RE... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-11-13	Alistair Francis	hw/riscv/virt: Free the test device tree node name Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-11-08	Alistair Francis	riscv: spike: Fix memory leak in the board init Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-09-05	Alistair Francis	hw/riscv/spike: Set the soc device tree node as a simple-bus Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-09-05	Alistair Francis	hw/riscv/virtio: Set the soc device tree node as a... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-19	Alistair Francis	spike: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-19	Alistair Francis	riscv_hart: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-19	Alistair Francis	virt: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-19	Alistair Francis	sifive_u: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-19	Alistair Francis	sifive_e: Fix crash when introspecting the device Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_u: Connect the Cadence GEM Ethernet... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_u: Move the uart device tree node under... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_u: Set the interrupt controller number... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_u: Set the soc device tree node as... Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_plic: Use gpios instead of irqs Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_e: Create a SiFive E SoC object Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-07-05	Alistair Francis	hw/riscv/sifive_u: Create a SiFive U SoC object Signed-off-by: Alistair Francis <alistair.francis@wdc.com>	commit \| commitdiff \| tree
2018-03-09	Alistair Francis	hw/arm: Set the core count for Xilinx's ZynqMP Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
2018-03-09	Alistair Francis	target/arm: Add a core count property Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
2018-03-02	Alistair Francis	xlnx-zynqmp: Connect the RTC device Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
2018-03-02	Alistair Francis	xlnx-zynqmp-rtc: Add basic time support Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
2018-03-02	Alistair Francis	xlnx-zynqmp-rtc: Initial commit Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>	commit \| commitdiff \| tree
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