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RISC-V: Add misa runtime write support
2019-02-11
Michael Clark
RISC-V: Add misa ru
n
time write s
u
p
p
o
rt
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2019-02-11
Mic
h
ael Clark
RISC-V: Add misa
.
MAFD checks to tr
a
ns
l
ate
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2019-02-11
Michael Cl
a
rk
R
ISC-V: Add
m
isa to DisasConte
x
t
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2019-02-11
Michael Clark
RISC-V: Use
r
i
s
cv pr
e
fix
consistent
l
y on cp
u
helpers
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2019-02-11
Mi
c
hae
l
Clar
k
RISC
-
V: Imp
l
e
m
ent mstatus
.
TSR/TW/TVM
Signed-off-by: Michael Clark <
mjc@sifive.com
>
Co-authored-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2019-01-09
Michael
C
l
ark
RISC-V:
I
m
p
lemen
t
existential pred
i
cates for
CSRs
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2019-01-09
Michael
C
lark
RISC-V: Im
p
lement a
t
omic mip/sip CSR up
d
ates
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2019-01-08
Michael Cla
r
k
R
IS
C
-V: Imp
l
ement modular CSR helper interface
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
M
i
chael
Clark
RISC-V: Enable s
e
cond UART
on sifiv
e
_e and sifive_u
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-12-20
M
i
chael
C
lark
RISC-V: F
i
x
PLIC
p
ending bitfield
r
eads
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-12-20
Micha
e
l Clark
RIS
C
-V
:
Fix CLINT timecmp low 32-bit writ
e
s
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-12-20
Michael Clark
RISC-V: Add hartid and \n
to interr
u
pt lo
g
g
ing
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-10-17
Mi
c
h
ael C
l
ark
RISC-V
:
D
o
n't add NULL bootargs t
o
d
evi
c
e-tree
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
M
i
chael
C
lark
RISC-V:
Add
missing fre
e
for plic
_
ha
r
t
_config
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Mich
a
e
l
Clark
RISC-
V
: Update CSR and interr
u
pt def
i
nitions
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-10-17
M
i
chael Clark
RI
S
C-V: Mo
v
e non-ops from op_helper to cpu_helper
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-10-17
Michael
C
la
r
k
RISC-V
:
Allow settin
g
and clearing
m
ulti
p
le irqs
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-09-04
Mi
c
hael Clark
RISC
-
V
:
S
i
mpli
f
y ris
c
v_
c
pu
_
l
o
cal_irqs_pendi
n
g
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-09-04
M
i
chael Clark
RISC-V: Us
e
atomic_cmpxchg to update
PLIC
b
itm
a
ps
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-09-04
Micha
e
l Clark
RISC-V: Impr
o
ve page table
w
alker spec compli
a
nc
e
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-09-04
Micha
e
l
Cl
a
rk
RISC-V: U
p
date
a
d
d
ress bits to
s
upport sv39 and
sv48
commit
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commitdiff
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2018-05-05
Michael
C
lar
k
RISC-V: Mark ROM rea
d
-o
n
ly after
c
opying in co
d
e
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
ichael
C
lark
RISC-V: No traps o
n
wr
i
tes
to misa,minstret,
m
cycle
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael C
l
ark
RISC-
V
:
M
ake mtvec/stvec i
g
nore vec
t
o
r
ed traps
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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2018-05-05
M
ich
a
el
C
l
ark
RISC-
V
:
A
dd mcycle/minstret suppo
r
t for -icount auto
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael Cla
r
k
RISC-V: Use
[
ms]counte
r
en C
S
R
s w
h
en priv ISA >= v1
.
10
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
M
i
chael
Clark
R
I
SC-V: Allo
w
S-mod
e
mxr access when priv ISA >= v1
.
1
0
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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2018-05-05
M
i
c
hael Clark
RISC-V: Clear mtval/stval
o
n ex
c
e
p
t
ions wit
h
ou
t
info
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Michael
C
l
ar
k
RISC-V:
Hardw
i
re
satp to 0 for no-mmu case
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-05-05
Mich
a
el
C
l
a
r
k
RISC-V: Update E and I ext
e
nsion
o
rder
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael
C
la
r
k
RISC-V: Remo
v
e erroneous comment from trans
l
at
e
.
c
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: Remove
E
M_RISCV ELF_MACHINE
i
n
d
irectio
n
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Cla
r
k
RISC-V: Make
v
i
rt header co
m
m
ent title consistent
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l Clark
RISC-V: Make some
header guards more specific
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clar
k
RI
S
C-V: Fix mis
s
ing break statement in
disa
s
sembler
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael
C
lark
R
I
SC-V
:
Includ
e
i
nst
r
uc
t
io
n
hex in dis
a
ss
e
mb
l
y
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Cl
a
rk
RISC-V: Remo
v
e unus
e
d class defin
i
t
ions
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hael
C
lark
RISC-V: Rem
o
v
e
ident
i
ty_tr
a
ns
l
a
te from load_elf
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l
C
lark
RISC-V: Use ROM base add
r
e
ss
a
nd siz
e
f
r
om memmap
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Mi
c
hael Cla
r
k
R
ISC-V: Make virt board
d
escriptio
n
match spike
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-05-05
Michael
C
l
ark
RISC-V: Replace ha
r
dcoded
c
onstants with e
n
um values
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-29
Mich
a
el
Clark
RISC-V: Workaround for
critica
l
m
status
.
FS bug
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-28
Michael Clark
R
ISC-V: Fix
i
ncorre
c
t disass
e
mbly for addi
w
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-28
Michael Clark
RISC-V
:
Conv
e
rt cpu d
e
f
inition t
o
futur
e
model
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-20
M
ich
a
el Cl
a
rk
RISC-V: Fix
riscv_isa
_
string memory size bug
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
RISC-V Build In
f
rastruc
t
u
r
e
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
a
rk
SiFive Fre
e
dom U Se
r
ies RISC-V
Machine
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Cla
r
k
SiFive F
r
e
e
dom E Series RISC-V
Machine
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
Clark
SiFiv
e
RISC-V PRCI Blo
c
k
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
Si
F
ive
R
IS
C
-V U
A
RT De
v
ice
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ael
C
lark
RI
S
C-V VirtIO
Ma
c
h
i
ne
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el
C
l
ark
SiFive
R
ISC-V Test Finisher
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
l
a
rk
RISC-V Spike Machines
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael
C
la
r
k
SiFive R
I
SC-V PLIC Blo
c
k
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
icha
e
l Clark
SiFive RISC-V CLINT B
l
ock
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
ichael
C
lark
RI
S
C-
V
HART Array
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clar
k
RISC-V HTIF Console
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clar
k
Add symbo
l
table
c
a
llback int
e
r
fac
e
to load_elf
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC
-
V
L
i
nux User
E
mu
l
ation
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mic
h
ae
l
Clark
RISC-
V
Physical Mem
o
ry P
r
otec
t
i
o
n
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael C
l
ark
RISC-
V
TCG Code Genera
t
ion
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
h
a
el Clar
k
RISC-V GDB Stub
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
I
SC-V FPU
S
upport
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mich
a
el
Clark
RISC-V CPU
Helpers
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michae
l
Clark
RISC-V Disassembler
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
M
icha
e
l
Clark
RISC-V
CPU Core
Definiti
o
n
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
hael Clark
RISC-V ELF Machi
n
e Definitio
n
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
ISC-V Maintainers
Signed-off-by: Michael Clark <
mjc@sifive.com
>
commit
|
commitdiff
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tree