| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: floating-point move instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-38-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: integer scalar move instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-37-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: register gather instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-36-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: allow load element with sign... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-35-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: element index instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-34-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: iota instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-33-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: set-X-first mask bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-32-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: find-first-set mask bit instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-31-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: count population in mask instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-30-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: floating-point classify instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-29-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: floating-point square-root instruction Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-28-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: take fractional LMUL into vector... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-27-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: update vext_max_elems() for... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-26-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: load/store whole register instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-25-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: fault-only-first unit stride... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-24-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: fix address index overflow bug... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-23-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: index load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-22-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: stride load and store instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-21-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: configure instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-20-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: remove amo operations instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-19-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv:1.0: add translation-time nan-box... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-18-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: introduce more imm value modes in translator... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-17-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: update check functions Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-16-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: add VMA and VTA Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-15-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: add fractional LMUL Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-14-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: remove MLEN calculations Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-13-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: check MSTATUS_VS when accessing... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211210075704.23951-12-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: remove rvv related codes from... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-9-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: add translation-time vector... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-8-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: introduce writable misa.v field Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-7-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: rvv-1.0: set mstatus.SD bit if mstatus... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-5-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: Use FIELD_EX32() to extract wd field Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-3-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: drop vector 0.7.1 and add 1.0 support Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20211210075704.23951-2-frank.chang@sifive.com> |
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| 2021-12-20 | Frank Chang | target/riscv: zfh: add Zfhmin cpu property Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20211210074329.5775-9-frank.chang@sifive.com |
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| 2021-12-20 | Frank Chang | target/riscv: zfh: implement zfhmin extension Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20211210074329.5775-8-frank.chang@sifive.com |
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| 2021-12-20 | Frank Chang | target/riscv: zfh: add Zfh cpu property Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20211210074329.5775-7-frank.chang@sifive.com |
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| 2021-10-21 | Frank Chang | target/riscv: fix TB_FLAGS bits overlapping bug for... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...Id: <20211015074627.3957162-2-frank.chang@sifive.com> |
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| 2021-10-21 | Frank Chang | target/riscv: Pass the same value to oprsz and maxsz... Signed-off-by: Frank Chang <frank.chang@sifive.com> ...id: 20211007081803.1705656-1-frank.chang@sifive.com |
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| 2021-10-06 | Frank Chang | target/riscv: Set mstatus_hs.[SD|FS] bits if Clean... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210921020234.123448-1-frank.chang@sifive.com |
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| 2021-09-21 | Frank Chang | target/riscv: Backup/restore mstatus.SD bit when virtual... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210914013717.881430-1-frank.chang@sifive.com |
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| 2021-09-20 | Frank Chang | hw/dma: sifive_pdma: don't set Control.error if 0 bytes... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-5-frank.chang@sifive.com |
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| 2021-09-20 | Frank Chang | hw/dma: sifive_pdma: claim bit must be set before DMA... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-3-frank.chang@sifive.com |
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| 2021-09-20 | Frank Chang | hw/dma: sifive_pdma: reset Next* registers when Control... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210912130553.179501-2-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: rvb: add b-ext version cpu option Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-18-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: rvb: generalized or-combine Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-14-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: rvb: generalized reverse Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-13-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: rvb: single-bit instructions Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-10-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: add gen_shifti() and gen_shiftiw() helper... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-9-frank.chang@sifive.com |
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| 2021-06-07 | Frank Chang | target/riscv: rvb: count bits set Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210505160620.15723-4-frank.chang@sifive.com |
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| 2021-05-11 | Frank Chang | fpu/softfloat: set invalid excp flag for RISC-V muladd... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210420013150.21992-1-frank.chang@sifive.com |
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| 2021-05-11 | Frank Chang | target/riscv: fix vrgather macro index variable type bug Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210419060302.14075-1-frank.chang@sifive.com |
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| 2021-03-23 | Frank Chang | target/riscv: fix vs() to return proper error code Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-id: 20210223065935.20208-1-frank.chang@sifive.com |
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| 2020-08-28 | Frank Chang | softfloat: Add fp16 and uint8/int8 conversion functions Signed-off-by: Frank Chang <frank.chang@sifive.com> |
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| 2020-07-14 | Frank Chang | target/riscv: fix vill bit index in vtype register Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-5-frank.chang@sifive.com> |
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| 2020-07-14 | Frank Chang | target/riscv: fix return value of do_opivx_widen() Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-4-frank.chang@sifive.com> |
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| 2020-07-14 | Frank Chang | target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-3-frank.chang@sifive.com> |
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| 2020-07-14 | Frank Chang | target/riscv: fix rsub gvec tcg_assert_listed_vecop... Signed-off-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20200710104920.13550-2-frank.chang@sifive.com> |
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