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RISC-V: Implement existential predicates for CSRs
2019-01-09
Michael Clar
k
R
ISC-V: Impleme
n
t existential predicat
e
s for C
S
Rs
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-01-09
Mic
h
ael Cla
r
k
RISC-V: Implement atomi
c
m
i
p/sip CSR updates
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2019-01-08
Michael C
l
a
r
k
RISC-V: Impl
e
ment
modular
C
SR helpe
r
i
n
terface
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-12-20
Michael Clark
RISC-V:
E
nable sec
o
nd U
A
RT on sifive_e and sifive_u
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-12-20
M
i
chael Clark
RISC-V: Fix PLIC pe
n
ding
b
i
t
fiel
d
r
e
ads
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-12-20
Michael Clark
RISC-V:
F
ix CLINT timecmp low 32-bit writes
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-12-20
M
ichael Clark
RISC-V: Add hartid
an
d
\n to
i
nt
e
rrupt logging
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-10-17
Mic
h
a
e
l
Clark
RISC-
V
: D
o
n't add NU
L
L bootargs
t
o device-tree
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-10-17
Michael Clark
RISC-V
:
Add missing free
f
or plic_hart
_
co
n
f
i
g
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
Mich
a
el Clark
RISC-V: Update CSR a
n
d i
n
terrupt definitions
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-10-17
M
i
chael
C
lark
RIS
C
-V:
M
ove non-ops from o
p
_help
e
r
to cpu_helper
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-10-17
Micha
e
l Clark
RISC-V
:
Allow
setting and clearin
g
multiple irqs
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Michael C
l
ark
RISC-V: S
i
mplify r
i
scv_c
p
u_local_
i
rqs_pendin
g
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Mic
h
ael
C
lark
RISC-V: Use ato
m
ic_
c
m
p
x
ch
g
to upd
a
te PLIC bitmaps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
M
ichael Clark
RISC-V: Improv
e
pa
g
e tab
l
e walker sp
e
c com
p
liance
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-09-04
Michael
C
l
ark
RISC-V: Update address
bits to support
s
v39 and
s
v
4
8
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RI
S
C-V: Mark ROM rea
d
-only after c
o
py
i
ng in cod
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Micha
e
l Clark
RIS
C
-V: No traps on writ
e
s to misa
,
minstret,mcycle
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: Make
mtvec/stvec ignore vectore
d
traps
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
M
ichael Clark
R
IS
C
-V: Add mcy
c
le/minstr
e
t support fo
r
-icount auto
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
M
i
c
hae
l
Clark
RISC-V: Use [ms]counteren C
S
R
s when
p
r
i
v ISA >= v1
.
10
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michae
l
Clark
RI
S
C-V: Allow S-mode mxr acce
s
s when priv
ISA
>= v1
.
10
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Mich
a
el
C
l
ark
RISC-V: Clear mtva
l
/
stval on exceptions without info
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Cl
a
rk
RISC-V: Hardwire satp to 0
f
or no
-
mmu case
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
chael Clark
R
I
SC-V:
Update E an
d
I
extension order
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: Remove
erroneous commen
t
from translate
.
c
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
RISC-V: Remove EM_RISCV
E
L
F
_M
A
CHINE indir
e
ction
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Mich
a
el Cla
r
k
RI
S
C-V: Make v
i
r
t header c
o
mment title consisten
t
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RISC
-
V: Make some header
guards more specific
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michael Clark
R
ISC-V: Fix missing bre
a
k
statement
i
n disassemb
l
e
r
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michae
l
Clark
RISC-V: Includ
e
instruc
t
i
o
n h
e
x
in disassembly
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RISC
-
V: Remov
e
unus
e
d class definiti
o
ns
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michael Clark
RISC-
V
:
R
emove
i
dentity_translate from load_elf
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
Michae
l
Clark
RISC-V:
U
se ROM
base address and size from memmap
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-05-05
Michael C
l
ark
R
I
S
C-V: Make virt board descriptio
n
match
s
pike
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-05-05
M
i
c
h
ael
Clar
k
RISC-V: Replace
hardc
o
ded
c
onstants with enum value
s
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-29
Micha
e
l Clark
RISC-V
:
Workarou
n
d for critica
l
mstatus
.
FS bug
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-28
Michael Clark
RISC-V: Fix i
n
c
o
rrect dis
a
ssembly
for addiw
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-28
Michael Cla
r
k
R
I
SC
-
V: C
o
nvert cpu definitio
n
to future model
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-20
M
ichael Clark
RISC-V: Fix riscv_isa_string m
e
m
o
ry
s
iz
e
b
u
g
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ich
a
el Clark
RISC-V Build Infrastructu
r
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
SiFive Freed
o
m
U
Serie
s
R
ISC-V Machine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Clark
S
i
F
i
ve Freedom E Seri
e
s
RISC-V M
a
chine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
ich
a
e
l
Clark
SiFive
R
I
S
C
-V PRCI
B
loc
k
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
S
iFive RISC-V UART
Devi
c
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael
Cl
a
rk
RISC-V
V
irtIO
Mac
h
ine
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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2018-03-06
Michael Clark
Si
F
ive RISC-V T
e
st Finisher
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
M
i
chael Cl
a
rk
RISC-V Spik
e
Mac
h
ines
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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2018-03-06
Mic
h
ael Clark
S
i
Five RISC-V PLIC Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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2018-03-06
Michael Clark
SiFi
v
e R
I
SC-V CLINT Block
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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2018-03-06
Mich
a
el Clark
RISC-V HART Ar
r
ay
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
RISC
-
V HTIF Con
s
o
l
e
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael
C
lar
k
Ad
d
symbol tabl
e
callback
inter
f
ace
to load_el
f
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l
Cla
r
k
RISC-V Linux User E
m
ula
t
ion
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Michael Clark
R
I
S
C-
V
P
hysical Memory Protectio
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Micha
e
l Cl
a
rk
RISC-V TCG C
o
de Genera
t
i
on
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Mich
a
el Clark
RISC-V
GDB Stub
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
Mi
c
hael
Clark
RIS
C
-V FPU Sup
p
o
r
t
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
RISC-V
CPU Helpers
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
|
tree
2018-03-06
M
i
chael Clark
RISC-V Disassembler
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
M
ichae
l
Clark
RISC-V
CPU Core Definit
i
on
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
M
i
chael C
l
a
r
k
RI
S
C-V EL
F
Machine Defin
i
ti
o
n
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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tree
2018-03-06
Michael Clark
RISC-V Main
t
ainers
Add
Michael Clark
, Palmer Dabbelt, Sagar Karandikar...
Signed-off-by:
Michael Clark
<mjc@sifive.com>
commit
|
commitdiff
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