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target/riscv/pmp: Add assert for ePMP operations
2021-06-07 Alistair Francistarget/riscv/pmp: Add assert for ePMP operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8c82fcb1f6805ee61dde82.1621550996.git.alistair.francis@wdc.com
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2021-06-07 Alistair Francisdocs/system: Move the RISC-V -bios information to removed
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...bb8926d85fe1d35e48ea5b.1620081256.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix the RV64H decode comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4b253512428c4baca7e4ba.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 16-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ebf133c2cde6a7a37224d7.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Consolidate RV32/64 32-bit instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c6483ab973fe4791aefa77.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove an unused CASE_OP_32_64 macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0120c74ad892f60cec35ff.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the unused HSTATUS_WPRI macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...822958f04dfc732d7beb7e.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...1739334198e36a64fe04df.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded MSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...817c9dd6068dc36478fc53.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded HGATP_MODE macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...265004b07de7489c77a766.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded SSTATUS_SD macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...172790f5b5fc058b40f2f1.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Remove the hardcoded RVXLEN macro
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...4f93cbc5d0acc31ed3344a.1619234854.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Add ePMP support for the Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2e989dbe416e417a551fd1.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv/pmp: Remove outdated comment
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9a78fdba85280cab4dd27f.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Add the ePMP feature
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c3ae009f5467e2b3960ce0.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix the PMP is locked check when using TOR
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...89bd59c59990247265b0c6.1618812899.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francishw/riscv: Enable VIRTIO_VGA for RISC-V virt machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0640f3233f8ad1ab270e1e.1617367317.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francishw/opentitan: Update the interrupt layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...10da2e9f23c414db5a6960.1617202791.git.alistair.francis@wdc.com
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2021-05-11 Alistair FrancisMAINTAINERS: Update the RISC-V CPU Maintainers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d28f43be69d8eb5cf4b56b.1617749142.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use RISCVException enum for CSR access
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...11b351b5c9f43039ca8ea3.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR operations
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ae8fc2429f906a459f17ce.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Fix 32-bit HS mode access permissions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Use the RISCVException enum for CSR predicates
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5aa482adb2a558c02a7cad.1617290165.git.alistair.francis@wdc.com
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2021-05-11 Alistair Francistarget/riscv: Convert the RISC-V exceptions to an enum
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e743a7c7f824d68879a527.1617290165.git.alistair.francis@wdc.com
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2021-03-04 Alistair FrancisMAINTAINERS: Add a SiFive machine section
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com
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2021-02-13 Alistair Francislinux-user/signal: Decode waitid si_code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3e638abe9e2d78c09a3d5b.1611080607.git.alistair.francis@wdc.com>
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2021-01-16 Alistair Francisriscv: Pass RISCVHartArrayState by pointer
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...69991896cc82308fd23f76.1610751609.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv/opentitan: Update the OpenTitan memory layout
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a3fccf77bc45b8ddd01c42.1607982831.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Use the CPU to determine if 32-bit
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...7788b73dcd75f9f5615e82.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Set XLEN independently from target
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...031431849fdd42eceb514b.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: csr: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3a1da21d03d33499c2beb0.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu_helper: Remove compile time XLEN...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...55d677e911b9432eb8f340.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: cpu: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...90066d43e91245683509d7.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Specify the XLEN for CPUs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...fbeb0194293bd24d65f5dc.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a riscv_cpu_is_32bit() helper function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...35b948bd57f487b6b31869.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: fpu_helper: Match function defs in HELPER...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...73a647b8aac7e023cba145.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: sifive_u: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e419be3a1fef7799e57c2e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: spike: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e421a0fcd9ac8a92014607.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: virt: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...aa0d41716238b055f3f25c.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: boot: Remove compile time XLEN checks
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ad7f97bd3aae69aa1ac19e.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: virt: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a5bd8f524d68795b12c0e4.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisriscv: spike: Remove target macro conditionals
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6a5e6a9959ac72b77ae4c6.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francistarget/riscv: Add a TYPE_RISCV_CPU_BASE CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...257679c6ccf6078a5d51af.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francishw/riscv: Expand the is 32-bit check to support more...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a61b56526c6de65fc3ef42.1608142916.git.alistair.francis@wdc.com
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2020-12-18 Alistair Francisintc/ibex_plic: Clear interrupts that occur during...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9123cc8a7837af8fa071cf.1607100423.git.alistair.francis@wdc.com
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2020-11-17 Alistair Francisregister: Remove unnecessary NULL check
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-11-14 Alistair Francisintc/ibex_plic: Ensure we don't loose interrupts
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...828e7c3f85293a09a65b12.1605136387.git.alistair.francis@wdc.com
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2020-11-14 Alistair Francisintc/ibex_plic: Fix some typos in the comments
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...67ac909926368d1bcb7cf5.1605136387.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francishw/intc/ibex_plic: Clear the claim register when read
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...747f3bda193fcf43af4558.1604629928.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Split the Hypervisor execute load helpers
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...77f3c1ae811dea98ab9e36.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the hyp load and store functions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...d18aad7074c6649f17de2c.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Remove the HS_TWO_STAGE flag
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...85f914cee18f905007a922.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Set the virtualised MMU mode when doing...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...53f13cac2fb86dc91ebee8.1604464950.git.alistair.francis@wdc.com
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2020-11-09 Alistair Francistarget/riscv: Add a virtualised MMU Mode
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...c1605371b65019ac3073df.1604464950.git.alistair.francis@wdc.com
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2020-11-04 Alistair Francislinux-user/syscall: Fix missing target_to_host_timespec64...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6b94acd9c34b00081c89bf.1604432881.git.alistair.francis@wdc.com>
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2020-10-22 Alistair Francishw/riscv: Load the kernel after the firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2090e3d74359e180a6d954.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: Add a riscv_is_32_bit() function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...9356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: Return the end address of the loaded firmware
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3262248b040563716628b2.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francishw/riscv: sifive_u: Allow specifying the CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...0fb7a17f0acf2943381b6a.1602634524.git.alistair.francis@wdc.com
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2020-10-22 Alistair Francisriscv: Convert interrupt logs to use qemu_log_mask()
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...2711c3a0abb81208138c5e.1601652179.git.alistair.francis@wdc.com
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2020-09-25 Alistair Franciscore/register: Specify instance_size in the TypeInfo
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...61d266557d3173bf160524.1598376594.git.alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Support the Virtual Instruction fault
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...5cc0f4d4ac75cda682a8af.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Return the exception from invalid CSR...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...b992c5e0dcc2504a9000a7.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Support the v0.6 Hypervisor extension...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e0ab8c9c66a8672059ec96.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Only support little endian guests
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...8e407187f33c6437aeaaf9.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Only support a single VSXL length
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...750e96895d6813f131de4d.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Update the CSRs to the v0.6 Hyp extension
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...96c0994f1123fab143666a.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Update the Hypervisor trap return/entry
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...6e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com
...6e734f65860f601a5745bd.1597259519.git.alistair.francis@wdc.com>
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2020-08-25 Alistair Francistarget/riscv: Fix the interrupt cause code
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3275cdc3043ce35a1ed5c3.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Convert MSTATUS MTL to GVA
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a68524ed76e4b8683f10e2.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Don't allow guest to write to htinst
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...eef3b3bc4b53cb5d4ad194.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Do two-stage lookups on hlv/hlvx/hsv...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...950fbfad1508cfa82ce7f0.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Allow generating hlv/hlvx/hsv instructions
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...98dc84cb01d826751b6c14.1597259519.git.alistair.francis@wdc.com
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2020-08-25 Alistair Francistarget/riscv: Allow setting a two-stage lookup in the...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com
...e3151c509aaadefc3dcd3e.1597259519.git.alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Honour source priorities
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...a88e09a28206063cf85d48.1595655188.git.alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Don't allow repeat interrupts on...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...ab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com>
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2020-08-22 Alistair Francishw/intc: ibex_plic: Update the pending irqs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>
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2020-07-14 Alistair Francishw/char: Convert the Ibex UART to use the registerfields API
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com
...899e71c858d9f0a2a3395b.1594332223.git.alistair.francis@wdc.com>
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2020-07-14 Alistair Francishw/char: Convert the Ibex UART to use the qdev Clock...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...59ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com
...59ec161c1217b967d7e19d.1594332223.git.alistair.francis@wdc.com>
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2020-07-02 Alistair Francishw/riscv: Allow 64 bit access to SiFive CLINT
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
...39b444d3a46fe894a7804c.1593547870.git.alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Use a smaller guess size for no-MMU PMP
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Connect the UART device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Connect the PLIC device
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francishw/intc: Initial commit of lowRISC Ibex PLIC
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francishw/char: Initial commit of Ibex UART
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francisriscv/opentitan: Fix the ROM size
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Implement checks for hfence
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Move the hfence instructions to the rvh...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Report errors validating 2nd-stage PTEs
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francistarget/riscv: Set access as data_load when validating...
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-19 Alistair Francissifive_e: Support the revB machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francisriscv: Initial commit of OpenTitan machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Add the lowRISC Ibex CPU
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Don't set PMP feature in the cpu init
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Disable the MMU correctly
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Don't overwrite the reset vector
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francisriscv/boot: Add a missing header include
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francisriscv: sifive_e: Manually define the machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francisdocs: deprecated: Update the -bios documentation
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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2020-06-03 Alistair Francistarget/riscv: Drop support for ISA spec version 1.09.1
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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