| 2020-07-02 | LIU Zhiwei | target/riscv: vector narrowing integer right shift... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-16-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: vector single-width bit shift instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-15-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: vector bitwise logical instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-14-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: vector integer add-with-carry / subtract... Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-13-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: vector widening integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-12-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: vector single-width integer add and subtract Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-11-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add vector amo operations Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-10-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add fault-only-first unit stride load Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-9-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add vector index load and store instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-8-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add vector stride load and store instructions Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-7-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add an internals.h header Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-6-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add vector configure instruction Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-5-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: support vector extension csr Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-4-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: implementation-defined constant parameters Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-3-zhiwei_liu@c-sky.com> |
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| 2020-07-02 | LIU Zhiwei | target/riscv: add vector extension field in CPURISCVState Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-Id: <20200701152549.1218-2-zhiwei_liu@c-sky.com> |
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| 2020-04-29 | LIU Zhiwei | linux-user/riscv: fix up struct target_ucontext definition Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Message-id: 20200412020830.607-1-zhiwei_liu@c-sky.com Message-Id: <20200412020830.607-1-zhiwei_liu@c-sky.com> |
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