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target/riscv: rvv-1.0: single-width scaling shift instructions
2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width scaling shift instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening floating-point reduction...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width floating-point...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing fixed-point clip instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point slide instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: slide instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: mask-register logical instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point compare instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer comparison instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width saturating add...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: widening integer multiply-add...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: narrowing integer right shift...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer add-with-carry/subtract...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width bit shift instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: single-width averaging add and...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer extension instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: whole register move instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point scalar move instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point move instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: integer scalar move instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: register gather instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: allow load element with sign...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: element index instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: iota instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set-X-first mask bit instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: find-first-set mask bit instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: count population in mask instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point classify instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: floating-point square-root instruction
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: take fractional LMUL into vector...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update vext_max_elems() for...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: load/store whole register instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fault-only-first unit stride...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: fix address index overflow bug...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: index load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: stride load and store instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: configure instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove amo operations instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv:1.0: add translation-time nan-box...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: introduce more imm value modes in translator...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: update check functions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add VMA and VTA
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add fractional LMUL
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove MLEN calculations
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: check MSTATUS_VS when accessing...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: remove rvv related codes from...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: add translation-time vector...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: introduce writable misa.v field
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: rvv-1.0: set mstatus.SD bit if mstatus...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: Use FIELD_EX32() to extract wd field
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: drop vector 0.7.1 and add 1.0 support
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfhmin cpu property
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: zfh: implement zfhmin extension
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-12-20 Frank Changtarget/riscv: zfh: add Zfh cpu property
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-10-21 Frank Changtarget/riscv: fix TB_FLAGS bits overlapping bug for...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-10-21 Frank Changtarget/riscv: Pass the same value to oprsz and maxsz...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-10-06 Frank Changtarget/riscv: Set mstatus_hs.[SD|FS] bits if Clean...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-09-21 Frank Changtarget/riscv: Backup/restore mstatus.SD bit when virtual...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: don't set Control.error if 0 bytes...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: claim bit must be set before DMA...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-09-20 Frank Changhw/dma: sifive_pdma: reset Next* registers when Control...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: add b-ext version cpu option
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized or-combine
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: generalized reverse
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: single-bit instructions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: add gen_shifti() and gen_shiftiw() helper...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-06-07 Frank Changtarget/riscv: rvb: count bits set
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-05-11 Frank Changfpu/softfloat: set invalid excp flag for RISC-V muladd...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-05-11 Frank Changtarget/riscv: fix vrgather macro index variable type bug
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2021-03-23 Frank Changtarget/riscv: fix vs() to return proper error code
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-08-28 Frank Changsoftfloat: Add fp16 and uint8/int8 conversion functions
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix vill bit index in vtype register
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix return value of do_opivx_widen()
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: correct the gvec IR called in gen_vec_rsub16_i64()
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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2020-07-14 Frank Changtarget/riscv: fix rsub gvec tcg_assert_listed_vecop...
Signed-off-by: Frank Chang <frank.chang@sifive.com>
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