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Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"
2021-11-02 Philippe Mathieu... Revert "elf: Relax MIPS' elf_check_arch() to accept...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211101114800.2692157-1-f4bug@amsat.org>
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2021-11-02 BALATON Zoltanhw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-11-02 BALATON Zoltanusb/uhci: Replace pci_set_irq with qemu_set_irq
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-11-02 BALATON Zoltanusb/uhci: Disallow user creating a vt82c686-uhci-pci...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-11-02 BALATON Zoltanusb/uhci: Misc clean up
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Remove obsolete FCR0_HAS2008 comment on...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028212103.2126176-1-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Fix Loongson-3A4000 MSAIR config register
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211026180920.1085516-1-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Remove one MSA unnecessary decodetree...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-32-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Remove generic MSA opcode
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-31-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert CTCMSA opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-30-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert CFCMSA opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-29-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA MOVE.V opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-28-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA COPY_S and INSERT opcodes...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-27-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA COPY_U opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-26-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA ELM instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-25-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3R instruction format to decodetree...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-24-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3R instruction format to decodetree...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-23-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3R instruction format to decodetree...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-22-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3R instruction format to decodetree...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-21-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3RF instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-20-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 3RF instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-19-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA VEC instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-18-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 2R instruction format to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-17-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA FILL opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-16-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA 2RF instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-15-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA load/store instruction format...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-14-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA I8 instruction format to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-13-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA SHF opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-12-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA BIT instruction format to...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-11-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA I5 instruction format to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-10-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Convert MSA LDI opcode to decodetree
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-9-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-8-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Use enum definitions from CPUMIPSMSADataFormat...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-7-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Have check_msa_access() return a boolean
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-6-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Use dup_const() to simplify
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-5-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Adjust style in msa_translate_init()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211023214803.522078-34-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Fix MSA MSUBV.B opcode
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-3-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... target/mips: Fix MSA MADDV.B opcode
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211028210843.2120802-2-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... MAINTAINERS: Split MIPS TCG frontend vs MIPS machines...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211004092515.3819836-4-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211027041416.1237433-3-f4bug@amsat.org>
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2021-11-02 Philippe Mathieu... MAINTAINERS: Add MIPS general architecture support...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211004092515.3819836-2-f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/timer/sh_timer: Remove use of hw_error
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/timer/sh_timer: Fix timer memory region size
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/timer/sh_timer: Do not wrap lines that are not too...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/timer/sh_timer: Rename sh_timer_state to SHTimerState
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Remove unneeded local variable initialisers
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Simplify allocating sources array
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Avoid using continue in loops
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Replace abort() with g_assert_not_reached()
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Inline and drop sh_intc_source() function
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Use array index instead of pointer...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Remove excessive parenthesis
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Move sh_intc_register() closer to...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Drop another useless macro
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Rename iomem region
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Turn some defines into an enum
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/intc/sh_intc: Use existing macro instead of local one
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: Add device id to trace output
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: QOM-ify
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: Split off sh_serial_reset() from...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: Embed QEMUTimer in state struct
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: Rename type sh_serial_state to SHSerialState
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/char/sh_serial: Do not abort on invalid access
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4/r2d: Use error_report instead of fprintf to...
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Change debug printfs to traces
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Fix typos in a comment
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Coding style: Remove unnecessary casts
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Coding style: Add missing braces
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Coding style: White space fixes
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Coding style: Fix multi-line comments
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-30 BALATON Zoltanhw/sh4: Coding style: Remove tabs
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 BALATON Zoltanvia-ide: Avoid using isa_get_irq()
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 BALATON Zoltanvt82c686: Add a method to VIA_ISA to raise ISA interrupts
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 BALATON Zoltanvt82c686: Move common code to via_isa_realize
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 BALATON Zoltanvia-ide: Set user_creatable to false
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Remove unused TCG temporary in gen_mipsdsp_acci...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211014224551.2204949-1-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Fix DEXTRV_S.H DSP opcode
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211013215652.1764551-1-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use tcg_constant_tl() in gen_compute_compact_br...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-9-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use explicit extract32() calls in gen_msa_i5()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-7-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use tcg_constant_i32() in gen_msa_3rf()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-6-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use tcg_constant_i32() in gen_msa_2r()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-5-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use tcg_constant_i32() in gen_msa_2rf()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-4-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Use tcg_constant_i32() in gen_msa_elm_df()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-3-f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Remove unused register from MSA 2R/2RF...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20211003175743.3738710-2-f4bug@amsat.org>
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2021-10-17 Jiaxun Yanghw/mips/boston: Add FDT generator
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 Jiaxun Yanghw/mips/boston: Allow loading elf kernel and dtb
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 Jiaxun Yanghw/mips/boston: Massage memory map information
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-10-17 Philippe Mathieu... target/mips: Check nanoMIPS DSP MULT[U] accumulator...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigend...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210818164321.2474534-6-f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Store CP0_Config0 in DisasContext
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210818164321.2474534-5-f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Replace GET_LMASK64() macro by get_lmask...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210818215517.2560994-4-f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Replace GET_LMASK() macro by get_lmask...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210818215517.2560994-3-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Call cpu_is_bigendian & inline GET_OFFSET...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210818215517.2560994-2-f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Define gen_helper() macros in translate.h
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-9-f4bug@amsat.org>
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2021-08-25 Philippe Mathieu... target/mips: Use tcg_constant_i32() in generate_exception_err()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-8-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Inline gen_helper_0e0i()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-7-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Inline gen_helper_1e1i() call in op_ld_INSN...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-6-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Simplify gen_helper() macros by using...
...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-5-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Use tcg_constant_i32() in gen_helper_0e2i()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-4-f4bug@amsat.org>
 commit | commitdiff | tree
2021-08-25 Philippe Mathieu... target/mips: Remove gen_helper_1e2i()
 ...off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
...Id: <20210816205107.2051495-3-f4bug@amsat.org>
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