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target/riscv: Support setting external interrupt by KVM
2022-01-21
Yifei Jiang
t
arget/riscv
:
Sup
p
o
rt
setting exter
n
a
l inter
r
upt
b
y
KVM
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Y
ifei Jian
g
target/riscv:
Support
s
tart kernel directly by KV
M
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Yi
f
ei Jia
n
g
target/r
i
scv
:
Implement kvm_arch_put
_
registers
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Yif
e
i Jia
n
g
target/riscv:
I
m
plement
k
vm_
a
rch_get_reg
i
sters
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Yifei
J
iang
ta
r
get/
r
is
c
v: Implement fu
n
ct
i
on kvm_
a
r
ch_init_vcpu
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Y
ifei
J
iang
target
/
r
iscv: Add t
a
rget/ri
s
cv/kvm
.
c to place the public
.
.
.
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2022-01-21
Yifei Jiang
u
p
date-l
i
n
u
x-headers: Add asm-risc
v
/kvm
.
h
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2021-03-04
Yifei Jiang
target-riscv
:
support
QMP dump-guest-me
m
o
r
y
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-12-18
Yi
f
ei
Jiang
target/riscv: Fix the bug of HLV
X
/HLV/HSV
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Yifei Jiang
t
a
rget/riscv: Add si
f
i
ve_plic vmstate
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Yifei
J
ia
n
g
ta
r
get
/
r
i
scv: Add V extensi
o
n
state desc
r
i
ption
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Yifei Jiang
target/riscv: Add
H ext
e
nsio
n
sta
t
e description
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Y
ifei Jiang
t
arget/riscv:
Add PMP
s
tate descript
i
on
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Yif
e
i
Ji
a
ng
ta
r
g
e
t/riscv: Add basi
c
vmstate
d
es
c
ript
i
o
n
of
C
PU
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-11-03
Y
i
fei Jiang
tar
g
et/riscv: Merge m/v
s
status and m/v
s
statush into
.
.
.
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-10-22
Yifei
J
i
ang
tar
g
et/
r
is
c
v: raise
exceptio
n
to H
S
-mode at get_physical_address
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree
2020-09-09
Y
ifei Ji
a
ng
target
/
riscv: Fix b
u
g in get
t
ing tr
a
p
ca
u
se name for
.
.
.
Signed-off-by:
Yifei Jiang
<jiangyifei@huawei.com>
commit
|
commitdiff
|
tree