From fdcc7c0631144933e955b6ddbbd10325abc7f688 Mon Sep 17 00:00:00 2001 From: Rashmica Gupta Date: Wed, 4 Sep 2019 09:04:58 +0200 Subject: [PATCH] aspeed: add a GPIO controller to the SoC MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Signed-off-by: Rashmica Gupta Reviewed-by: Cédric Le Goater Signed-off-by: Cédric Le Goater Message-id: 20190904070506.1052-3-clg@kaod.org Signed-off-by: Peter Maydell --- hw/arm/aspeed_soc.c | 17 +++++++++++++++++ include/hw/arm/aspeed_soc.h | 3 +++ 2 files changed, 20 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 9ee8104832..04480875d0 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -125,6 +125,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .spis_num = 1, .fmc_typename = "aspeed.smc.fmc", .spi_typename = aspeed_soc_ast2400_typenames, + .gpio_typename = "aspeed.gpio-ast2400", .wdts_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, @@ -137,6 +138,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .spis_num = 1, .fmc_typename = "aspeed.smc.fmc", .spi_typename = aspeed_soc_ast2400_typenames, + .gpio_typename = "aspeed.gpio-ast2400", .wdts_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, @@ -149,6 +151,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .spis_num = 1, .fmc_typename = "aspeed.smc.fmc", .spi_typename = aspeed_soc_ast2400_typenames, + .gpio_typename = "aspeed.gpio-ast2400", .wdts_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, @@ -161,6 +164,7 @@ static const AspeedSoCInfo aspeed_socs[] = { .spis_num = 2, .fmc_typename = "aspeed.smc.ast2500-fmc", .spi_typename = aspeed_soc_ast2500_typenames, + .gpio_typename = "aspeed.gpio-ast2500", .wdts_num = 3, .irqmap = aspeed_soc_ast2500_irqmap, .memmap = aspeed_soc_ast2500_memmap, @@ -247,6 +251,9 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), TYPE_ASPEED_XDMA); + + sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), + sc->info->gpio_typename); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -426,6 +433,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sc->info->memmap[ASPEED_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, aspeed_soc_get_irq(s, ASPEED_XDMA)); + + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_soc_get_irq(s, ASPEED_GPIO)); } static Property aspeed_soc_properties[] = { DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 976fd6be93..a56effebc1 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -23,6 +23,7 @@ #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" +#include "hw/gpio/aspeed_gpio.h" #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 3 @@ -48,6 +49,7 @@ typedef struct AspeedSoCState { AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; + AspeedGPIOState gpio; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -61,6 +63,7 @@ typedef struct AspeedSoCInfo { int spis_num; const char *fmc_typename; const char **spi_typename; + const char *gpio_typename; int wdts_num; const int *irqmap; const hwaddr *memmap; -- 2.11.4.GIT