From e45868a3f30a1fdf22bdee8b503b71d8f642f0f4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 20 Jan 2017 11:15:09 +0000 Subject: [PATCH] target-arm: Add ARMCPU fields for GIC CPU i/f config Add fields to the ARMCPU structure to allow CPU classes to specify the configurable aspects of their GIC CPU interface. In particular, the virtualization support allows different values for number of list registers, priority bits and preemption bits. Signed-off-by: Peter Maydell Acked-by: Alistair Francis Message-id: 1483977924-14522-6-git-send-email-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/cpu64.c | 6 ++++++ 2 files changed, 11 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fa09498939..16c7c10bfb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -662,6 +662,11 @@ struct ARMCPU { uint32_t dcz_blocksize; uint64_t rvbar; + /* Configurable aspects of GIC cpu interface (which is part of the CPU) */ + int gic_num_lrs; /* number of list registers */ + int gic_vpribits; /* number of virtual priority bits */ + int gic_vprebits; /* number of virtual preemption bits */ + ARMELChangeHook *el_change_hook; void *el_change_hook_opaque; }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 549cb1ee93..73c7f318ec 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -147,6 +147,9 @@ static void aarch64_a57_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */ cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } @@ -201,6 +204,9 @@ static void aarch64_a53_initfn(Object *obj) cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */ cpu->dcz_blocksize = 4; /* 64 bytes */ + cpu->gic_num_lrs = 4; + cpu->gic_vpribits = 5; + cpu->gic_vprebits = 5; define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo); } -- 2.11.4.GIT