From 0b572c8131998e7bcd048dbbbe78f95e6101d68d Mon Sep 17 00:00:00 2001 From: Weiwei Li Date: Mon, 18 Jul 2022 21:09:50 +0800 Subject: [PATCH] target/riscv: Add check for supported privilege mode combinations There are 3 suggested privilege mode combinations listed in section 1.2 of the riscv-privileged spec(draft-20220717): 1) M, 2) M, U 3) M, S, U Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Reviewed-by: Andrew Jones Message-Id: <20220718130955.11899-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a3e4e2477f..b919ad9056 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -721,6 +721,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; -- 2.11.4.GIT