| commit | bff384a4fbd5d0e86939092e74e766ef0f5f592c | |
| author | Leon Alrae <leon.alrae@imgtec.com> | |
| Tue, 15 Mar 2016 09:59:35 +0000 (15 09:59 +0000) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Wed, 30 Mar 2016 08:13:59 +0000 (30 09:13 +0100) | ||
| tree | fc9325844e57fe16f7fd3165c2dd55de6e60f8e6 | treesnapshot (tar.gz zip) |
| parent | 67a54961848cd78a82ef23b26a0daf011c1f5d4d | commitdiff |
hw/mips_malta: add CPS to Malta board
If the user specifies smp > 1 and the CPU with CM GCR support, then
create Coherent Processing System (which takes care of instantiating CPUs)
rather than CPUs directly and connect i8259 and cbus to the pins exposed by
CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use
the same pin numbers as before.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
If the user specifies smp > 1 and the CPU with CM GCR support, then
create Coherent Processing System (which takes care of instantiating CPUs)
rather than CPUs directly and connect i8259 and cbus to the pins exposed by
CPS. However, there is no GIC yet, thus CPS exposes CPU's IRQ pins so use
the same pin numbers as before.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| hw/mips/mips_malta.c | diffblobblamehistory | |
| target-mips/cpu.h | diffblobblamehistory | |
| target-mips/translate.c | diffblobblamehistory |