| commit | fe8fcf3d642b4de1369841bf6acac13e0ec8770d | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 14 Jun 2016 14:59:15 +0000 (14 15:59 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 14 Jun 2016 15:01:03 +0000 (14 16:01 +0100) | ||
| tree | 2c41b2e3abf67957ea1b75e7d5330ab2b1dff4fe | treesnapshot (tar.gz zip) |
| parent | b93dbcdd5993dd0800d18d494f60821a398fee8b | commitdiff |
target-arm: Don't permit ARMv8-only Neon insns on ARMv7
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
so they need a guard to make them UNDEF if the CPU only supports ARMv7.
(We got this right for all the other new-in-v8 insns, but forgot
it for these Neon 2-reg-misc ops.)
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1465492511-9333-1-git-send-email-peter.maydell@linaro.org
The Neon instructions VCVTA, VCVTM, VCVTN, VCVTP, VRINTA, VRINTM,
VRINTN, VRINTP, VRINTX, and VRINTZ were only introduced with ARMv8,
so they need a guard to make them UNDEF if the CPU only supports ARMv7.
(We got this right for all the other new-in-v8 insns, but forgot
it for these Neon 2-reg-misc ops.)
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
Tested-by: Christophe Lyon <christophe.lyon@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1465492511-9333-1-git-send-email-peter.maydell@linaro.org
| target-arm/translate.c | diffblobblamehistory |