| commit | cfc2a2d69d59f02b32df3098ce17e10ab86d43c6 | |
| author | Idan Horowitz <idan.horowitz@gmail.com> | |
| Mon, 10 Jan 2022 16:47:53 +0000 (10 18:47 +0200) | ||
| committer | Richard Henderson <richard.henderson@linaro.org> | |
| Tue, 8 Feb 2022 21:55:02 +0000 (9 08:55 +1100) | ||
| tree | 04bfc4cb798c32cdd8572cdfb55c0bea57c3303a | treesnapshot (tar.gz zip) |
| parent | 4f152ef27e26d82905244b7cbe344929630d8fae | commitdiff |
accel/tcg: Optimize jump cache flush during tlb range flush
When the length of the range is large enough, clearing the whole cache is
faster than iterating over the (possibly extremely large) set of pages
contained in the range.
This mimics the pre-existing similar optimization done on the flush of the
tlb itself.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
When the length of the range is large enough, clearing the whole cache is
faster than iterating over the (possibly extremely large) set of pages
contained in the range.
This mimics the pre-existing similar optimization done on the flush of the
tlb itself.
Signed-off-by: Idan Horowitz <idan.horowitz@gmail.com>
Message-Id: <20220110164754.1066025-1-idan.horowitz@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
| accel/tcg/cputlb.c | diffblobblamehistory |