| commit | cedf706956e7440653b18ac2c2a9452b8d710577 | |
| author | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Mon, 18 Oct 2021 01:01:22 +0000 (17 22:01 -0300) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Thu, 21 Oct 2021 00:42:47 +0000 (21 11:42 +1100) | ||
| tree | 3664a9a7ee24c076316f7a37275679756c6306be | treesnapshot (tar.gz zip) |
| parent | 7b3ecf16c81c16eb3cf171b0bd63c08f1a5dd942 | commitdiff |
target/ppc: adding user read/write functions for PMCs
Problem state needs to be able to read and write the PMU counters,
otherwise it won't be aware of any sampling result that the PMU produces
after a Perf run.
This patch does that in a similar fashion as already done in the
previous patches. PMCs 5 and 6 have a special condition, aside from the
constraints that are common with PMCs 1-4, where they are not part of the
PMU if MMCR0_PMCC is 0b11.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-5-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Problem state needs to be able to read and write the PMU counters,
otherwise it won't be aware of any sampling result that the PMU produces
after a Perf run.
This patch does that in a similar fashion as already done in the
previous patches. PMCs 5 and 6 have a special condition, aside from the
constraints that are common with PMCs 1-4, where they are not part of the
PMU if MMCR0_PMCC is 0b11.
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211018010133.315842-5-danielhb413@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/cpu_init.c | diffblobblamehistory | |
| target/ppc/power8-pmu-regs.c.inc | diffblobblamehistory | |
| target/ppc/spr_tcg.h | diffblobblamehistory |