| commit | ce4fcb94785f7326682e1c72400ddd299481db6e | |
| author | Paolo Bonzini <pbonzini@redhat.com> | |
| Fri, 2 Sep 2022 16:19:06 +0000 (2 18:19 +0200) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Tue, 18 Oct 2022 11:58:05 +0000 (18 13:58 +0200) | ||
| tree | 7c45788c7e822d03b81a8ed6a00cba10da88219f | treesnapshot (tar.gz zip) |
| parent | d1c1a4222cdcab0e3de1635dbc71dc646975507b | commitdiff |
target/i386: reimplement 0x0f 0x70-0x77, add AVX
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh then this
would be one of the starting points. The implementation of the VZEROALL
and VZEROUPPER helpers is by Paul Brook.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This includes shifts by immediate, which use bits 3-5 of the ModRM byte
as an opcode extension. With the exception of 128-bit shifts, they are
implemented using gvec.
This also covers VZEROALL and VZEROUPPER, which use the same opcode
as EMMS. If we were wanting to optimize out gen_clear_ymmh then this
would be one of the starting points. The implementation of the VZEROALL
and VZEROUPPER helpers is by Paul Brook.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| target/i386/tcg/decode-new.c.inc | diffblobblamehistory | |
| target/i386/tcg/emit.c.inc | diffblobblamehistory | |
| target/i386/tcg/translate.c | diffblobblamehistory |