| commit | cc7613bfaa1f653a6eb6ff50ac45d5c5fd717052 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 16 Aug 2021 18:03:04 +0000 (16 19:03 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 26 Aug 2021 16:02:01 +0000 (26 17:02 +0100) | ||
| tree | 542ec7f1f8e56ec4555ecd4c8fa3c4a173b6632e | treesnapshot (tar.gz zip) |
| parent | 665cddbe15fdc5f5c66caac62472bd5af1e23e10 | commitdiff |
target/arm: Implement HSTR.TTEE
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses
to the Thumb2EE TEECR and TEEHBR registers to be trapped to the
hypervisor. Implement these traps.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
In v7, the HSTR register has a TTEE bit which allows EL0/EL1 accesses
to the Thumb2EE TEECR and TEEHBR registers to be trapped to the
hypervisor. Implement these traps.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210816180305.20137-2-peter.maydell@linaro.org
| target/arm/cpu.h | diffblobblamehistory | |
| target/arm/helper.c | diffblobblamehistory |