target-arm: Add AArch64 CPTR registers
commitc6f191642a4027909813b4e6e288411f8371e951
authorGreg Bellows <greg.bellows@linaro.org>
Fri, 29 May 2015 10:28:52 +0000 (29 11:28 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Fri, 29 May 2015 10:28:52 +0000 (29 11:28 +0100)
treec2ad623d9938b41924b431ac4b381bf64bc5670c
parent38836a2cd47c20daaaa84873e3d6020f19e4bfca
target-arm: Add AArch64 CPTR registers

Adds CPTR_EL2/3 system registers definitions and access function.

Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
[PMM: merge CPTR_EL2 and HCPTR definitions into a single
 def using STATE_BOTH;
 don't use readfn/writefn to implement RAZ/WI registers;
 don't use accessfn for the no-EL2 CPTR_EL2;
 fix cpacr_access logic to catch EL2 accesses to CPACR being
 trapped to EL3;
 use new CP_ACCESS_TRAP_EL[23] rather than setting
 exception.target_el directly]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
target-arm/cpu.h
target-arm/helper.c