target-mips: Correct 32-bit address space wrapping
commitc48245f0c62405f27266fcf08722d8c290520418
authorMaciej W. Rozycki <macro@codesourcery.com>
Wed, 19 Nov 2014 17:29:00 +0000 (19 17:29 +0000)
committerLeon Alrae <leon.alrae@imgtec.com>
Tue, 16 Dec 2014 12:45:20 +0000 (16 12:45 +0000)
tree4d08bee9257ebc937b5bc0a18935a4f9e064ba25
parentd9224450208e0de62323b64ace91f98bc31d6e2c
target-mips: Correct 32-bit address space wrapping

Make sure the address space is unconditionally wrapped on 32-bit
processors, that is ones that do not implement at least the MIPS III
ISA.

Also make MIPS16 SAVE and RESTORE instructions use address calculation
rather than plain arithmetic operations for stack pointer manipulation
so that their semantics for stack accesses follows the architecture
specification.  That in particular applies to user software run on
64-bit processors with the CP0.Status.UX bit clear where the address
space is wrapped to 32 bits.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
target-mips/cpu.h
target-mips/translate.c