| commit | c3513c836e4c19cd7a2a7f691995fdef587cec72 | |
| author | Richard Henderson <richard.henderson@linaro.org> | |
| Wed, 27 Jun 2018 15:40:23 +0000 (27 08:40 -0700) | ||
| committer | Stafford Horne <shorne@gmail.com> | |
| Mon, 2 Jul 2018 13:31:59 +0000 (2 22:31 +0900) | ||
| tree | b503d5ad3b37a4fa9c85e591af9966c260d2e1e8 | treesnapshot (tar.gz zip) |
| parent | 646f34fa5482e495483de230b4cf0f2ae4fd2781 | commitdiff |
target/openrisc: Fix mtspr shadow gprs
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
| target/openrisc/sys_helper.c | diffblobblamehistory |