| commit | bbfb6f132abc032229f5c1f25e6e959861c6f759 | |
| author | Tom Musta <tommusta@gmail.com> | |
| Wed, 25 Sep 2013 07:42:46 +0000 (25 17:42 +1000) | ||
| committer | Alexander Graf <agraf@suse.de> | |
| Fri, 25 Oct 2013 21:25:45 +0000 (25 23:25 +0200) | ||
| tree | b7a4fdb8428be4ae74620c06ac7ebd88f1ac0360 | treesnapshot (tar.gz zip) |
| parent | 04f1f7842e18c4b5e50203cc5b207cafb7c62974 | commitdiff |
target-ppc: Little Endian Correction to Load/Store Vector Element
The Load Vector Element (lve*x) and Store Vector Element (stve*x)
instructions not only byte-swap in Little Endian mode, they also
invert the element that is accessed. For example, the RTL for
lvehx contains this:
eb <-- EA[60:63]
if Big-Endian byte ordering then
VRT[8*eb:8*eb+15] <-- MEM(EA,2)
else
VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)
This patch adds the element inversion, as described in the last line
of the RTL.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
The Load Vector Element (lve*x) and Store Vector Element (stve*x)
instructions not only byte-swap in Little Endian mode, they also
invert the element that is accessed. For example, the RTL for
lvehx contains this:
eb <-- EA[60:63]
if Big-Endian byte ordering then
VRT[8*eb:8*eb+15] <-- MEM(EA,2)
else
VRT[112-(8*eb):127-(8*eb)] <-- MEM(EA,2)
This patch adds the element inversion, as described in the last line
of the RTL.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Reviewed-by: Anton Blanchard <anton@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
| target-ppc/mem_helper.c | diffblobblamehistory |