| commit | b137fb72d7f41a8c7e4dacbd0394612420db6c5d | |
| author | Fabiano Rosas <farosas@linux.ibm.com> | |
| Fri, 17 Dec 2021 16:57:16 +0000 (17 17:57 +0100) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Fri, 17 Dec 2021 16:57:16 +0000 (17 17:57 +0100) | ||
| tree | 68a11b2f84af94a84f4968c4a9d698cb5d72c64f | treesnapshot (tar.gz zip) |
| parent | 1da666cd8e795295e23f6feac7cf8d06f9c64725 | commitdiff |
target/ppc: Disable unused facilities in the e600 CPU
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
The e600 CPU is a successor of the 7448 and like all the 7450s CPUs,
it has an optional software TLB feature.
We have determined that there is no OS software support for the 7450
software TLB available these days. See the previous commit for more
information.
This patch disables the SPRs and instructions related to software TLB
from the e600 CPU.
No functional change intended. These facilities should be used by the
OS in interrupt handlers for interrupts that QEMU never generates.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20211130230123.781844-3-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| target/ppc/cpu_init.c | diffblobblamehistory |