| commit | af453a5ef58d21fa902aea9b6e4bc2312ac0467f | |
| author | Cédric Le Goater <clg@kaod.org> | |
| Thu, 10 Dec 2020 11:11:03 +0000 (10 12:11 +0100) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Thu, 10 Dec 2020 11:11:03 +0000 (10 12:11 +0100) | ||
| tree | 95f431d386a1e038288e2c8a3e536ead192b7986 | treesnapshot (tar.gz zip) |
| parent | e01b4d5b6ec9dbdd1ff31002fca0183f4ea2bf79 | commitdiff |
aspeed/smc: Add support for address lane disablement
The controller can be configured to disable or enable address and data
byte lanes when issuing commands. This is useful in read command mode
to send SPI NOR commands that don't have an address space, such as
RDID. It's a good way to have a unified read operation for registers
and flash contents accesses.
A new SPI driver proposed by Aspeed makes use of this feature. Add
support for address lanes to start with. We will do the same for the
data lanes if they are controlled one day.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20201120161547.740806-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
The controller can be configured to disable or enable address and data
byte lanes when issuing commands. This is useful in read command mode
to send SPI NOR commands that don't have an address space, such as
RDID. It's a good way to have a unified read operation for registers
and flash contents accesses.
A new SPI driver proposed by Aspeed makes use of this feature. Add
support for address lanes to start with. We will do the same for the
data lanes if they are controlled one day.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Message-Id: <20201120161547.740806-2-clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/ssi/aspeed_smc.c | diffblobblamehistory |