| commit | a984e42c916ad5afdf3f8660f284857547943aa4 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 17 Mar 2014 16:31:47 +0000 (17 16:31 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Mon, 17 Mar 2014 16:31:47 +0000 (17 16:31 +0000) | ||
| tree | cd3e835f0f03c47c328bb5a4e03a8b082a9306de | treesnapshot (tar.gz zip) |
| parent | d6d60581f3f6778de85ee23427006151b5226667 | commitdiff |
target-arm: A64: Implement PMULL instruction
Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.
Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org
Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.
Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org