ppc: Use split I/D mmu modes to avoid flushes on interrupts
commit9fb044911444fdd09f5f072ad0ca269d7f8b841d
authorBenjamin Herrenschmidt <benh@kernel.crashing.org>
Tue, 3 May 2016 16:03:24 +0000 (3 18:03 +0200)
committerDavid Gibson <david@gibson.dropbear.id.au>
Mon, 30 May 2016 03:20:04 +0000 (30 13:20 +1000)
treece608f84663764e368d651a5713933bb2c2127fd
parent5fd1111b20a8f1955e3156a80e0576007548e871
ppc: Use split I/D mmu modes to avoid flushes on interrupts

We rework the way the MMU indices are calculated, providing separate
indices for I and D side based on MSR:IR and MSR:DR respectively,
and thus no longer need to flush the TLB on context changes. This also
adds correct support for HV as a separate address space.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
target-ppc/cpu.h
target-ppc/excp_helper.c
target-ppc/helper_regs.h
target-ppc/machine.c
target-ppc/translate.c