| commit | 9390255468e33811e6791d5afef3113a40770aba | |
| author | Ben Widawsky <ben.widawsky@intel.com> | |
| Mon, 26 Oct 2020 19:39:24 +0000 (26 12:39 -0700) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Fri, 30 Oct 2020 08:29:13 +0000 (30 04:29 -0400) | ||
| tree | 121c597bbb46bcf83ae87473af7d63df6f5c89d7 | treesnapshot (tar.gz zip) |
| parent | acab9d8a9e31cc85ec95e5432500575680e7f07b | commitdiff |
acpi/crs: Support ranges > 32b for hosts
According to PCIe spec 5.0 Type 1 header space Base Address Registers
are defined by 7.5.1.2.1 Base Address Registers (same as Type 0). The
_CRS region should allow for the same range (up to 64b). Prior to this
change, any host bridge utilizing more than 32b for the BAR would have
the address truncated and likely lead to conflicts when the operating
systems reads the _CRS object.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Message-Id: <20201026193924.985014-2-ben.widawsky@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
According to PCIe spec 5.0 Type 1 header space Base Address Registers
are defined by 7.5.1.2.1 Base Address Registers (same as Type 0). The
_CRS region should allow for the same range (up to 64b). Prior to this
change, any host bridge utilizing more than 32b for the BAR would have
the address truncated and likely lead to conflicts when the operating
systems reads the _CRS object.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Message-Id: <20201026193924.985014-2-ben.widawsky@intel.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
| hw/i386/acpi-build.c | diffblobblamehistory |