| commit | 8e18cde30b06d2e7411bf38091c4e30602f85cdd | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 15 Mar 2011 16:26:51 +0000 (15 16:26 +0000) | ||
| committer | Aurelien Jarno <aurelien@aurel32.net> | |
| Fri, 1 Apr 2011 20:33:47 +0000 (1 22:33 +0200) | ||
| tree | b1c36d400bf36f68b0d20a29492b9aa383c71d9b | treesnapshot (tar.gz zip) |
| parent | ac60cc18711a9786af9844d7e3d002276fbd85f3 | commitdiff |
target-arm: Fix VLD of single element to all lanes
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register
stride). Handle this by special-casing VLD1 rather than trying to
have one loop which deals with both VLD1 and 2/3/4.
Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing.
UNDEF for the invalid size and alignment combinations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix several bugs in VLD of single element to all lanes:
The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register
stride). Handle this by special-casing VLD1 rather than trying to
have one loop which deals with both VLD1 and 2/3/4.
Handle VLD4.32 with 16 byte alignment specified, rather than UNDEFfing.
UNDEF for the invalid size and alignment combinations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| target-arm/translate.c | diffblobblamehistory |