| commit | 880f8486503b32a29b653a3c0b3cfc5432012f38 | |
| author | Paolo Bonzini <pbonzini@redhat.com> | |
| Tue, 1 Mar 2016 15:12:14 +0000 (1 16:12 +0100) | ||
| committer | Richard Henderson <rth@twiddle.net> | |
| Mon, 14 Mar 2016 17:52:29 +0000 (14 10:52 -0700) | ||
| tree | e804f6fab9c346b8ab29e33ae19a10f886d40676 | treesnapshot (tar.gz zip) |
| parent | 8b33e82b863d1c6fce7e69a41f6c96a8e15b73fb | commitdiff |
target-i386: Fix SMSW and LMSW from/to register
SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386:
Rearrange processing of 0F 01", 2016-02-13) did not account for that.
Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1
Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386:
Rearrange processing of 0F 01", 2016-02-13) did not account for that.
Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1
Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <1456845134-18812-1-git-send-email-pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
| target-i386/translate.c | diffblobblamehistory |