| commit | 87462e0f41fccc353f9c902caed563ab7cbdd8ed | |
| author | Claudio Fontana <claudio.fontana@linaro.org> | |
| Tue, 17 Dec 2013 19:42:32 +0000 (17 19:42 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 17 Dec 2013 19:42:32 +0000 (17 19:42 +0000) | ||
| tree | aad41097ea2f30dcf7cfbb19dab823dc0443373a | treesnapshot (tar.gz zip) |
| parent | ad7ee8a290d08a2fe9d408af2461d1f583d96f7d | commitdiff |
target-arm: A64: expand decoding skeleton for system instructions
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, which move from a gp register to a system register
mrs, which move from a system register to a gp register
Provide implementations where they are trivial nops.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync instructions, which include CLREX, DSB, DMB, ISB
msr_i, which move immediate to processor state field
sys, which include all SYS and SYSL instructions
msr, which move from a gp register to a system register
mrs, which move from a system register to a gp register
Provide implementations where they are trivial nops.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| target-arm/translate-a64.c | diffblobblamehistory |