| commit | 845d27a91315bc1e3a0000339c5ee46ef63598a5 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 23 Jul 2021 16:21:46 +0000 (23 17:21 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 27 Jul 2021 09:57:39 +0000 (27 10:57 +0100) | ||
| tree | c1be3d17724288dbb02d179b580ba9ebfadaa62f | treesnapshot (tar.gz zip) |
| parent | 7caad65756c0afaf4b238b068ab61481eb68a1dc | commitdiff |
hw/intc/armv7m_nvic: for v8.1M VECTPENDING hides S exceptions from NS
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
the register is accessed NonSecure and the highest priority pending
enabled exception (that would be returned in the VECTPENDING field)
targets Secure, then the VECTPENDING field must read 1 rather than
the exception number of the pending exception. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
In Arm v8.1M the VECTPENDING field in the ICSR has new behaviour: if
the register is accessed NonSecure and the highest priority pending
enabled exception (that would be returned in the VECTPENDING field)
targets Secure, then the VECTPENDING field must read 1 rather than
the exception number of the pending exception. Implement this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210723162146.5167-7-peter.maydell@linaro.org
| hw/intc/armv7m_nvic.c | diffblobblamehistory |