| commit | 829f9fd394ab082753308cbda165c13eaf8fae49 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 24 Aug 2018 12:17:38 +0000 (24 13:17 +0100) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 24 Aug 2018 12:17:38 +0000 (24 13:17 +0100) | ||
| tree | 328181ff25aab96c0527765a09e10ae4d385d1c5 | treesnapshot (tar.gz zip) |
| parent | b9bc21ff9f9bb2d841adf1dc7f6f8ddfb9ab8b5e | commitdiff |
target/arm: Clear CPSR.IL and CPSR.J on 32-bit exception entry
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180820153020.21478-6-peter.maydell@linaro.org
On 32-bit exception entry, CPSR.J must always be set to 0
(see v7A Arm ARM DDI0406C.c B1.8.5). CPSR.IL must also
be cleared on 32-bit exception entry (see v8A Arm ARM
DDI0487C.a G1.10).
Clear these bits. (This fixes a bug which will never be noticed
by non-buggy guests.)
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20180820153020.21478-6-peter.maydell@linaro.org
| target/arm/helper.c | diffblobblamehistory |