target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event
commit7aeac354a6925afcec684e985d56e612f9e81b2d
authorDaniel Henrique Barboza <danielhb413@gmail.com>
Fri, 17 Dec 2021 16:57:18 +0000 (17 17:57 +0100)
committerCédric Le Goater <clg@kaod.org>
Fri, 17 Dec 2021 16:57:18 +0000 (17 17:57 +0100)
tree77ed79d085d0a471f9f2ea1d9edad7814ef30ae2
parent46d396bde988020528445691089711eb27b348b5
target/ppc/power8-pmu.c: add PM_RUN_INST_CMPL (0xFA) event

PM_RUN_INST_CMPL, instructions completed with the run latch set, is
the architected PowerISA v3.1 event defined with PMC4SEL = 0xFA.

Implement it by checking for the CTRL RUN bit before incrementing the
counter. To make this work properly we also need to force a new
translation block each time SPR_CTRL is written. A small tweak in
pmu_increment_insns() is then needed to only increment this event
if the thread has the run latch.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20211201151734.654994-8-danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/cpu.h
target/ppc/cpu_init.c
target/ppc/power8-pmu.c
target/ppc/spr_tcg.h
target/ppc/translate.c