| commit | 6e8801f9dea9e10449f4fd7d85dbe8cab708a686 | |
| author | Fabian Aggeler <aggelerf@ethz.ch> | |
| Thu, 11 Dec 2014 12:07:50 +0000 (11 12:07 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Thu, 11 Dec 2014 12:07:50 +0000 (11 12:07 +0000) | ||
| tree | a5ef60f3661ba2ba765380f561ff05ce5ff1fba3 | treesnapshot (tar.gz zip) |
| parent | 137feaa9a1622620adf19c0b707883dd990738e2 | commitdiff |
target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-15-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Add checks of SCR AW/FW bits when performing writes of CPSR. These SCR bits
are used to control whether the CPSR masking bits can be adjusted from
non-secure state.
Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch>
Signed-off-by: Greg Bellows <greg.bellows@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1416242878-876-15-git-send-email-greg.bellows@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| target-arm/helper.c | diffblobblamehistory |