| commit | 645d843ca55f0a7aa9be3ef19694d5a44b002f6e | |
| author | Fabiano Rosas <farosas@linux.ibm.com> | |
| Fri, 28 Jan 2022 12:15:03 +0000 (28 13:15 +0100) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Fri, 28 Jan 2022 12:15:03 +0000 (28 13:15 +0100) | ||
| tree | 3a19bbb1fa3db0cb98bdb7d995bb94164b6f346b | treesnapshot (tar.gz zip) |
| parent | 47822486f5e7d6dad8d9a2381d127a831a3c5c11 | commitdiff |
target/ppc: 405: Rename MSR_POW to MSR_WE
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Bit 13 is the Wait State Enable bit. Give it its proper name.
As far as I can see we don't do anything with MSR_POW for the 405, so
this change has no effect.
Suggested-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Message-Id: <20220118184448.852996-2-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| target/ppc/cpu.h | diffblobblamehistory | |
| target/ppc/cpu_init.c | diffblobblamehistory |