| commit | 6364adacdfa6a24e3f5b08f6b5ffa789a5d828a7 | |
| author | Ben Widawsky <ben.widawsky@intel.com> | |
| Fri, 29 Apr 2022 14:40:30 +0000 (29 15:40 +0100) | ||
| committer | Michael S. Tsirkin <mst@redhat.com> | |
| Fri, 13 May 2022 10:13:36 +0000 (13 06:13 -0400) | ||
| tree | c6a6cd8f277bff7f6cc64489d0d3a49474a80286 | treesnapshot (tar.gz zip) |
| parent | cd90126b4ced427697d79eb5002544a7621ec647 | commitdiff |
hw/cxl/device: Implement the CAP array (8.2.8.1-2)
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignment are managed by softmmu memory core.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This implements all device MMIO up to the first capability. That
includes the CXL Device Capabilities Array Register, as well as all of
the CXL Device Capability Header Registers. The latter are filled in as
they are implemented in the following patches.
Endianness and alignment are managed by softmmu memory core.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-6-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
| hw/cxl/cxl-device-utils.c | [new file with mode: 0644] | blob |
| hw/cxl/meson.build | diffblobblamehistory | |
| include/hw/cxl/cxl_device.h | diffblobblamehistory |