target/riscv: rvv-1.0: add mstatus VS field
commit61b4b69d122c055fbf6310e629f3f2d1e70c2599
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Fri, 10 Dec 2021 07:55:49 +0000 (10 15:55 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 20 Dec 2021 04:51:36 +0000 (20 14:51 +1000)
tree584be60c06f2456326547d4d0f266b62e57552f7
parent52561f2a808a16bde80c9a165f54e07df2e527a7
target/riscv: rvv-1.0: add mstatus VS field

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20211210075704.23951-4-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c
target/riscv/csr.c