| commit | 5007c904e158aaaf97e65338e52f5ef9e8df0944 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 15 Feb 2019 09:56:39 +0000 (15 09:56 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Fri, 15 Feb 2019 09:56:39 +0000 (15 09:56 +0000) | ||
| tree | ab90266c344f9460be2bd424661cf991ba6dcfe9 | treesnapshot (tar.gz zip) |
| parent | 935fe442dc234c7b3fa52d346ced7a614696107e | commitdiff |
hw/arm/armsse: Fix miswiring of expansion IRQs
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
to external IRQ 1 on CPU 1.
Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
In commit 91c1e9fcbd7548db368 where we added dual-CPU support to
the ARMSSE, we set up the wiring of the expansion IRQs via nested
loops: the outer loop on 'i' loops for each CPU, and the inner loop
on 'j' loops for each interrupt. Fix a typo which meant we were
wiring every expansion IRQ line to external IRQ 0 on CPU 0 and
to external IRQ 1 on CPU 1.
Fixes: 91c1e9fcbd7548db368 ("hw/arm/armsse: Support dual-CPU configuration")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
| hw/arm/armsse.c | diffblobblamehistory |