| commit | 4b65b6e76977895fe43eb340c54b552fd16fe1ce | |
| author | Víctor Colombo <victor.colombo@eldorado.org.br> | |
| Tue, 6 Sep 2022 12:55:22 +0000 (6 09:55 -0300) | ||
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | |
| Tue, 20 Sep 2022 13:54:06 +0000 (20 10:54 -0300) | ||
| tree | 98926f490498cc53f582359b17b153880f6e11c4 | treesnapshot (tar.gz zip) |
| parent | af721a31696a1e08d8dcdabcd14c4cb09f9a5e16 | commitdiff |
target/ppc: Zero second doubleword of VSR registers for FPR insns
FPR register are mapped to the first doubleword of the VSR registers.
Since PowerISA v3.1, the second doubleword of the target register
must be zeroed for FP instructions.
This patch does it by writting 0 to the second dw everytime the
first dw is being written using set_fpr.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
FPR register are mapped to the first doubleword of the VSR registers.
Since PowerISA v3.1, the second doubleword of the target register
must be zeroed for FP instructions.
This patch does it by writting 0 to the second dw everytime the
first dw is being written using set_fpr.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220906125523.38765-8-victor.colombo@eldorado.org.br>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
| target/ppc/translate.c | diffblobblamehistory |