| commit | 4700a316df7d2cdcd256dcd64a10cec643f4dfa1 | |
| author | Paolo Bonzini <pbonzini@redhat.com> | |
| Tue, 5 Mar 2013 14:04:36 +0000 (5 15:04 +0100) | ||
| committer | Paolo Bonzini <pbonzini@redhat.com> | |
| Tue, 13 May 2014 11:22:29 +0000 (13 13:22 +0200) | ||
| tree | f51f9f50e9514558cc4d7cc9a166968596eabfbd | treesnapshot (tar.gz zip) |
| parent | 4a92a558f49cb0693e36bd6d4f9217f298045be2 | commitdiff |
pc: port 92 reset requires a low->high transition
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.
This bug is masked right now because a full reset will clear the
value of port 92h. But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
The PIIX datasheet says that "before another INIT pulse can be
generated via [port 92h], [bit 0] must be written back to a
zero.
This bug is masked right now because a full reset will clear the
value of port 92h. But once we implement soft reset correctly,
the next attempt to enable the A20 line by setting bit 1 (and
leaving the others untouched) will cause another reset.
Reviewed-by: Anthony Liguori <aliguori@us.ibm.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| hw/i386/pc.c | diffblobblamehistory |