| commit | 3e6a417c8a077595ebcb4fb1d0944b291564cd43 | |
| author | Atish Patra <atishp@rivosinc.com> | |
| Thu, 3 Mar 2022 18:54:38 +0000 (3 10:54 -0800) | ||
| committer | Alistair Francis <alistair.francis@wdc.com> | |
| Fri, 22 Apr 2022 00:35:16 +0000 (22 10:35 +1000) | ||
| tree | 567b368877681ae53ca7120bef828b91fcc87cb3 | treesnapshot (tar.gz zip) |
| parent | a4b2fa433125af0305b0695d7f8dda61db3364b0 | commitdiff |
target/riscv: Add support for mconfigptr
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
RISC-V privileged specification v1.12 introduced a mconfigptr
which will hold the physical address of a configuration data
structure. As Qemu doesn't have a configuration data structure,
is read as zero which is valid as per the priv spec.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-Id: <20220303185440.512391-5-atishp@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
| target/riscv/cpu_bits.h | diffblobblamehistory | |
| target/riscv/csr.c | diffblobblamehistory |